Console Output

+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p Risco-5 -b digilent_arty_a7_100t -l
Final configuration file generated at /var/jenkins_home/workspace/Risco-5/Risco-5/build_digilent_arty_a7_100t.tcl
Makefile executed successfully.
Makefile output:
Flashing the FPGA...
/eda/oss-cad-suite/bin/openFPGALoader -b arty_a7_100t digilent_arty_a7_100t.bit
empty
Jtag frequency : requested 10.00MHz   -> real 10.00MHz  
Open file DONE
Parse file DONE
load program

Load SRAM: [===============                                   ] 30.00%
Load SRAM: [===============================                   ] 62.00%
Load SRAM: [===============================================   ] 94.00%
Load SRAM: [===================================================] 100.00%
Done
Shift IR 35
ir: 1 isc_done 1 isc_ena 0 init 1 done 1