+ echo Test for FPGA in /dev/ttyACM0
Test for FPGA in /dev/ttyACM0
[Pipeline] sh
+ python3 /eda/processor_ci_tests/test_runner/run.py --config /eda/processor_ci_tests/test_runner/config.json --port /dev/ttyACM0
Running tests in {'name': 'RV32I', 'path': '/eda/processor_ci_tests/tests/RV32I'}
Error loading test /eda/processor_ci_tests/tests/RV32I/advanced/memory/014-beq.hex: invalid literal for int() with base 16: '# Reference data for beq\n'
Error loading test /eda/processor_ci_tests/tests/RV32I/advanced/memory/035-or.hex: invalid literal for int() with base 16: '# Reference data for or\n'
Error loading test /eda/processor_ci_tests/tests/RV32I/advanced/memory/038-ecall.hex: invalid literal for int() with base 16: '# Reference data for ecall\n'
Error loading test /eda/processor_ci_tests/tests/RV32I/advanced/memory/012-jal.hex: invalid literal for int() with base 16: '# Reference data for jal\n'
Error loading test /eda/processor_ci_tests/tests/RV32I/advanced/memory/017-bge.hex: invalid literal for int() with base 16: '# Reference data for bge\n'
Error loading test /eda/processor_ci_tests/tests/RV32I/advanced/memory/004-xori.hex: invalid literal for int() with base 16: '# Reference data for xori\n'
Error loading test /eda/processor_ci_tests/tests/RV32I/advanced/memory/025-sb.hex: invalid literal for int() with base 16: '# Reference data for sb\n'
Error loading test /eda/processor_ci_tests/tests/RV32I/advanced/memory/001-sw.hex: invalid literal for int() with base 16: '# Reference data for sw\n'
Error loading test /eda/processor_ci_tests/tests/RV32I/advanced/memory/029-sll.hex: invalid literal for int() with base 16: '# Reference data for sll\n'
Error loading test /eda/processor_ci_tests/tests/RV32I/advanced/memory/013-jalr.hex: invalid literal for int() with base 16: '# Reference data for jalr\n'
Error loading test /eda/processor_ci_tests/tests/RV32I/advanced/memory/008-srli.hex: invalid literal for int() with base 16: '# Reference data for srli\n'
Error loading test /eda/processor_ci_tests/tests/RV32I/advanced/memory/005-ori.hex: invalid literal for int() with base 16: '# Reference data for ori\n'
Error loading test /eda/processor_ci_tests/tests/RV32I/advanced/memory/003-sltiu.hex: invalid literal for int() with base 16: '# Reference data for sltiu\n'
Error loading test /eda/processor_ci_tests/tests/RV32I/advanced/memory/024-lhu.hex: invalid literal for int() with base 16: '# Reference data for lhu\n'
Error loading test /eda/processor_ci_tests/tests/RV32I/advanced/memory/010-lui.hex: invalid literal for int() with base 16: '# Reference data for lui\n'
Error loading test /eda/processor_ci_tests/tests/RV32I/advanced/memory/022-lw.hex: invalid literal for int() with base 16: '# Reference data for lw\n'
Error loading test /eda/processor_ci_tests/tests/RV32I/advanced/memory/028-sub.hex: invalid literal for int() with base 16: '# Reference data for sub\n'
Error loading test /eda/processor_ci_tests/tests/RV32I/advanced/memory/039-ebreak.hex: invalid literal for int() with base 16: '# Reference data for ebreak\n'
Error loading test /eda/processor_ci_tests/tests/RV32I/advanced/memory/016-blt.hex: invalid literal for int() with base 16: '# Reference data for blt\n'
Error loading test /eda/processor_ci_tests/tests/RV32I/advanced/memory/018-bltu.hex: invalid literal for int() with base 16: '# Reference data for bltu\n'
Error loading test /eda/processor_ci_tests/tests/RV32I/advanced/memory/009-srai.hex: invalid literal for int() with base 16: '# Reference data for srai\n'
Error loading test /eda/processor_ci_tests/tests/RV32I/advanced/memory/036-and.hex: invalid literal for int() with base 16: '# Reference data for and\n'
Error loading test /eda/processor_ci_tests/tests/RV32I/advanced/memory/026-sh.hex: invalid literal for int() with base 16: '# Reference data for sh\n'
Error loading test /eda/processor_ci_tests/tests/RV32I/advanced/memory/015-bne.hex: invalid literal for int() with base 16: '# Reference data for bne\n'
Error loading test /eda/processor_ci_tests/tests/RV32I/advanced/memory/021-lh.hex: invalid literal for int() with base 16: '# Reference data for lh\n'
Error loading test /eda/processor_ci_tests/tests/RV32I/advanced/memory/006-andi.hex: invalid literal for int() with base 16: '# Reference data for andi\n'
Error loading test /eda/processor_ci_tests/tests/RV32I/advanced/memory/002-slti.hex: invalid literal for int() with base 16: '# Reference data for slti\n'
Error loading test /eda/processor_ci_tests/tests/RV32I/advanced/memory/032-xor.hex: invalid literal for int() with base 16: '# Reference data for xor\n'
Error loading test /eda/processor_ci_tests/tests/RV32I/advanced/memory/007-slli.hex: invalid literal for int() with base 16: '# Reference data for slli\n'
Error loading test /eda/processor_ci_tests/tests/RV32I/advanced/memory/037-fence.hex: invalid literal for int() with base 16: '# Reference data for fence\n'
Error loading test /eda/processor_ci_tests/tests/RV32I/advanced/memory/011-auipc.hex: invalid literal for int() with base 16: '# Reference data for auipc\n'
Error loading test /eda/processor_ci_tests/tests/RV32I/advanced/memory/033-srl.hex: invalid literal for int() with base 16: '# Reference data for srl\n'
Error loading test /eda/processor_ci_tests/tests/RV32I/advanced/memory/019-bgeu.hex: invalid literal for int() with base 16: '# Reference data for bgeu\n'
Error loading test /eda/processor_ci_tests/tests/RV32I/advanced/memory/027-add.hex: invalid literal for int() with base 16: '# Reference data for add\n'
Error loading test /eda/processor_ci_tests/tests/RV32I/advanced/memory/031-sltu.hex: invalid literal for int() with base 16: '# Reference data for sltu\n'
Error loading test /eda/processor_ci_tests/tests/RV32I/advanced/memory/034-sra.hex: invalid literal for int() with base 16: '# Reference data for sra\n'
Error loading test /eda/processor_ci_tests/tests/RV32I/advanced/memory/020-lb.hex: invalid literal for int() with base 16: '# Reference data for lb\n'
Error loading test /eda/processor_ci_tests/tests/RV32I/advanced/memory/030-slt.hex: invalid literal for int() with base 16: '# Reference data for slt\n'
Error loading test /eda/processor_ci_tests/tests/RV32I/advanced/memory/023-lbu.hex: invalid literal for int() with base 16: '# Reference data for lbu\n'
Error loading test /eda/processor_ci_tests/tests/RV32I/advanced/memory/000-addi.hex: invalid literal for int() with base 16: '# Reference data for addi\n'
Error loading test /eda/processor_ci_tests/tests/RV32I/invalid/memory/000-invalid1.hex: invalid literal for int() with base 16: '# Invalid reference placeholder 1\n'
Error loading test /eda/processor_ci_tests/tests/RV32I/invalid/memory/004-invalid5.hex: invalid literal for int() with base 16: '# Invalid reference placeholder 5\n'
Error loading test /eda/processor_ci_tests/tests/RV32I/invalid/memory/001-invalid2.hex: invalid literal for int() with base 16: '# Invalid reference placeholder 2\n'
Error loading test /eda/processor_ci_tests/tests/RV32I/invalid/memory/003-invalid4.hex: invalid literal for int() with base 16: '# Invalid reference placeholder 4\n'
Error loading test /eda/processor_ci_tests/tests/RV32I/invalid/memory/002-invalid3.hex: invalid literal for int() with base 16: '# Invalid reference placeholder 3\n'
Size: 14
Test 014-beq: False
Expected: 10, Actual: 0
False
0
0.10036969184875488
Size: 4
Test 035-or: False
Expected: 10, Actual: 18
False
18
0.10036849975585938
Size: 0
Test 038-ecall: False
Expected: 10, Actual: 18
False
18
0.1003255844116211
Size: 6
Test 012-jal: False
Expected: 10, Actual: 18
False
18
0.10108613967895508
Size: 14
Test 017-bge: False
Expected: 10, Actual: 18
False
18
0.10049819946289062
Size: 4
Test 004-xori: False
Expected: 10, Actual: 20
False
20
0.10033392906188965
Size: 5
Test 025-sb: False
Expected: 10, Actual: 4109
False
4109
0.10216712951660156
Size: 2
Test 001-sw: False
Expected: 10, Actual: 25
False
25
0.10035896301269531
Size: 8
Test 042-forwarding-lw: False
Expected: 10, Actual: 21
False
21
0.10032963752746582
Size: 4
Test 029-sll: False
Expected: 10, Actual: 2
False
2
0.10040712356567383
Size: 8
Test 013-jalr: False
Expected: 10, Actual: 8
False
8
0.10176491737365723
Size: 3
Test 008-srli: False
Expected: 10, Actual: 8
False
8
0.10042953491210938
Size: 3
Test 005-ori: False
Expected: 10, Actual: 8
False
8
0.10034894943237305
Size: 3
Test 003-sltiu: False
Expected: 10, Actual: 8
False
8
0.10033202171325684
Size: 0
Test 024-lhu: False
Expected: 10, Actual: 8
False
8
0.10031867027282715
Size: 2
Test 010-lui: False
Expected: 10, Actual: 8
False
8
0.10032439231872559
Size: 6
Test 022-lw: False
Expected: 10, Actual: 4104
False
4104
0.10031986236572266
Size: 4
Test 028-sub: False
Expected: 10, Actual: 2062
False
2062
0.10032153129577637
Size: 0
Test 039-ebreak: False
Expected: 10, Actual: 2062
False
2062
0.10044693946838379
Size: 14
Test 016-blt: False
Expected: 10, Actual: 2062
False
2062
0.10031414031982422
Size: 14
Test 018-bltu: False
Expected: 10, Actual: 2062
False
2062
0.10034966468811035
Size: 3
Test 009-srai: False
Expected: 10, Actual: 20
False
20
0.10034060478210449
Size: 4
Test 036-and: False
Expected: 10, Actual: 20
False
20
0.100372314453125
Size: 7
Test 041-forwarding: False
Expected: 10, Actual: 35
False
35
0.10047435760498047
Size: 5
Test 026-sh: False
Expected: 10, Actual: 131023
False
131023
0.10032081604003906
Size: 14
Test 015-bne: False
Expected: 10, Actual: 131023
False
131023
0.10030412673950195
Size: 6
Test 021-lh: False
Expected: 10, Actual: 262031
False
262031
0.10038352012634277
Size: 3
Test 006-andi: False
Expected: 10, Actual: 262036
False
262036
0.1003270149230957
Size: 5
Test 002-slti: False
Expected: 10, Actual: 6
False
6
0.10037732124328613
Size: 4
Test 032-xor: False
Expected: 10, Actual: 9
False
9
0.10031533241271973
Size: 3
Test 007-slli: False
Expected: 10, Actual: 12
False
12
0.10038423538208008
Size: 0
Test 037-fence: False
Expected: 10, Actual: 15
False
15
0.10033106803894043
Size: 3
Test 040-timeout: False
Expected: 10, Actual: 18
False
18
0.10137534141540527
Size: 5
Test 011-auipc: False
Expected: 10, Actual: 3657433110
False
3657433110
0.1003715991973877
Size: 4
Test 033-srl: False
Expected: 10, Actual: 3657433111
False
3657433111
0.10035133361816406
Size: 14
Test 019-bgeu: False
Expected: 10, Actual: 3657433111
False
3657433111
0.10033750534057617
Size: 3
Test 027-add: False
Expected: 10, Actual: 20
False
20
0.10038113594055176
Size: 4
Test 031-sltu: False
Expected: 10, Actual: 20
False
20
0.10104179382324219
Size: 4
Test 034-sra: False
Expected: 10, Actual: 20
False
20
0.10037803649902344
Size: 4
Test 020-lb: False
Expected: 10, Actual: 20
False
20
0.10033226013183594
Size: 4
Test 030-slt: False
Expected: 10, Actual: 20
False
20
0.10033416748046875
Size: 0
Test 023-lbu: False
Expected: 10, Actual: 20
False
20
0.10032415390014648
Size: 5
Test 000-addi: False
Expected: 10, Actual: 20
False
20
0.1003720760345459
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Lock released on resource [Resource: colorlight_i9]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Final configuration file generated at /var/jenkins_home/workspace/Risco-5/Risco-5/build_digilent_arty_a7_100t.tcl
Makefile executed successfully.
Makefile output:
Building the Design...
/eda/vivado/Vivado/2023.2/bin/vivado -mode batch -nolog -nojournal -source /var/jenkins_home/workspace/Risco-5/Risco-5/build_digilent_arty_a7_100t.tcl -tclargs "ID=0x6a6a6a6a" "CLOCK_FREQ=50000000" "MEMORY_SIZE=4096"
****** Vivado v2023.2 (64-bit)
**** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
**** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
**** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
source /var/jenkins_home/workspace/Risco-5/Risco-5/build_digilent_arty_a7_100t.tcl
# read_verilog /eda/processor_ci/rtl/Risco-5.v
read_verilog: Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 1308.113 ; gain = 0.023 ; free physical = 369 ; free virtual = 26194
# read_verilog /var/jenkins_home/workspace/Risco-5/Risco-5/src/core/alu.v
# read_verilog /var/jenkins_home/workspace/Risco-5/Risco-5/src/core/alu_control.v
# read_verilog /var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v
# read_verilog /var/jenkins_home/workspace/Risco-5/Risco-5/src/core/core.v
# read_verilog /var/jenkins_home/workspace/Risco-5/Risco-5/src/core/csr_unit.v
# read_verilog /var/jenkins_home/workspace/Risco-5/Risco-5/src/core/immediate_generator.v
# read_verilog /var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v
# read_verilog /var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mux.v
# read_verilog /var/jenkins_home/workspace/Risco-5/Risco-5/src/core/pc.v
# read_verilog /var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v
# read_verilog /eda/processor-ci-controller/modules/uart.v
# read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_rx.v
# read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_tx.v
# read_verilog /eda/processor-ci-controller/src/fifo.v
# read_verilog /eda/processor-ci-controller/src/reset.v
# read_verilog /eda/processor-ci-controller/src/clk_divider.v
# read_verilog /eda/processor-ci-controller/src/memory.v
# read_verilog /eda/processor-ci-controller/src/interpreter.v
# read_verilog /eda/processor-ci-controller/src/controller.v
# set ID [lindex $argv 0]
# set CLOCK_FREQ [lindex $argv 1]
# set MEMORY_SIZE [lindex $argv 2]
# set HIGH_CLK 1
# read_xdc "/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc"
# set_property PROCESSING_ORDER EARLY [get_files /eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]
# synth_design -top "processorci_top" -part "xc7a100tcsg324-1" -verilog_define $ID -verilog_define $CLOCK_FREQ -verilog_define $MEMORY_SIZE \
# -verilog_define $HIGH_CLK
Command: synth_design -top processorci_top -part xc7a100tcsg324-1 -verilog_define ID=0x6a6a6a6a -verilog_define CLOCK_FREQ=50000000 -verilog_define MEMORY_SIZE=4096 -verilog_define 1
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t'
INFO: [Device 21-403] Loading part xc7a100tcsg324-1
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 2388219
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 2031.812 ; gain = 403.660 ; free physical = 155 ; free virtual = 25060
---------------------------------------------------------------------------------
INFO: [Synth 8-11241] undeclared symbol 'reset_o', assumed default net type 'wire' [/eda/processor_ci/rtl/Risco-5.v:54]
WARNING: [Synth 8-8895] 'reset_o' is already implicitly declared on line 54 [/eda/processor_ci/rtl/Risco-5.v:143]
INFO: [Synth 8-11241] undeclared symbol 'pc_source', assumed default net type 'wire' [/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/core.v:197]
WARNING: [Synth 8-6901] identifier 'PAYLOAD_BITS' is used before its declaration [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:16]
WARNING: [Synth 8-6901] identifier 'PAYLOAD_BITS' is used before its declaration [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:16]
WARNING: [Synth 8-11065] parameter 'INIT' becomes localparam in 'ResetBootSystem' with formal parameter declaration list [/eda/processor-ci-controller/src/reset.v:15]
WARNING: [Synth 8-11065] parameter 'RESET_COUNTER' becomes localparam in 'ResetBootSystem' with formal parameter declaration list [/eda/processor-ci-controller/src/reset.v:16]
WARNING: [Synth 8-11065] parameter 'IDLE' becomes localparam in 'ResetBootSystem' with formal parameter declaration list [/eda/processor-ci-controller/src/reset.v:17]
WARNING: [Synth 8-6901] identifier 'bus_mode' is used before its declaration [/eda/processor-ci-controller/src/controller.v:84]
WARNING: [Synth 8-6901] identifier 'memory_page_number' is used before its declaration [/eda/processor-ci-controller/src/controller.v:85]
INFO: [Synth 8-6157] synthesizing module 'processorci_top' [/eda/processor_ci/rtl/Risco-5.v:1]
INFO: [Synth 8-6157] synthesizing module 'Controller' [/eda/processor-ci-controller/src/controller.v:1]
Parameter CLK_FREQ bound to: 50000000 - type: integer
Parameter BIT_RATE bound to: 115200 - type: integer
Parameter PAYLOAD_BITS bound to: 8 - type: integer
Parameter BUFFER_SIZE bound to: 8 - type: integer
Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer
Parameter BUS_WIDTH bound to: 32 - type: integer
Parameter WORD_SIZE_BY bound to: 4 - type: integer
Parameter ID bound to: 0 - type: integer
Parameter RESET_CLK_CYCLES bound to: 20 - type: integer
Parameter MEMORY_FILE bound to: (null) - type: string
Parameter MEMORY_SIZE bound to: 4096 - type: integer
INFO: [Synth 8-6157] synthesizing module 'ClkDivider' [/eda/processor-ci-controller/src/clk_divider.v:1]
Parameter COUNTER_BITS bound to: 32 - type: integer
Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'ClkDivider' (0#1) [/eda/processor-ci-controller/src/clk_divider.v:1]
INFO: [Synth 8-6157] synthesizing module 'Interpreter' [/eda/processor-ci-controller/src/interpreter.v:1]
Parameter CLK_FREQ bound to: 50000000 - type: integer
Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer
Parameter BUS_WIDTH bound to: 32 - type: integer
Parameter ID bound to: 0 - type: integer
Parameter RESET_CLK_CYCLES bound to: 20 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'Interpreter' (0#1) [/eda/processor-ci-controller/src/interpreter.v:1]
INFO: [Synth 8-6157] synthesizing module 'UART' [/eda/processor-ci-controller/modules/uart.v:1]
Parameter CLK_FREQ bound to: 50000000 - type: integer
Parameter BIT_RATE bound to: 115200 - type: integer
Parameter PAYLOAD_BITS bound to: 8 - type: integer
Parameter BUFFER_SIZE bound to: 8 - type: integer
Parameter WORD_SIZE_BY bound to: 4 - type: integer
INFO: [Synth 8-226] default block is never used [/eda/processor-ci-controller/modules/uart.v:213]
INFO: [Synth 8-6157] synthesizing module 'FIFO' [/eda/processor-ci-controller/src/fifo.v:1]
Parameter DEPTH bound to: 8 - type: integer
Parameter WIDTH bound to: 8 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'FIFO' (0#1) [/eda/processor-ci-controller/src/fifo.v:1]
INFO: [Synth 8-6157] synthesizing module 'uart_rx' [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:9]
Parameter BIT_RATE bound to: 115200 - type: integer
Parameter CLK_HZ bound to: 50000000 - type: integer
Parameter PAYLOAD_BITS bound to: 8 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'uart_rx' (0#1) [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:9]
INFO: [Synth 8-6157] synthesizing module 'uart_tx' [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:10]
Parameter BIT_RATE bound to: 115200 - type: integer
Parameter CLK_HZ bound to: 50000000 - type: integer
Parameter PAYLOAD_BITS bound to: 8 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'uart_tx' (0#1) [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:10]
INFO: [Synth 8-6155] done synthesizing module 'UART' (0#1) [/eda/processor-ci-controller/modules/uart.v:1]
INFO: [Synth 8-6157] synthesizing module 'Memory' [/eda/processor-ci-controller/src/memory.v:1]
Parameter MEMORY_FILE bound to: (null) - type: string
Parameter MEMORY_SIZE bound to: 4096 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'Memory' (0#1) [/eda/processor-ci-controller/src/memory.v:1]
WARNING: [Synth 8-7071] port 'read_sync' of module 'Memory' is unconnected for instance 'Data_Memory' [/eda/processor-ci-controller/src/controller.v:268]
WARNING: [Synth 8-7071] port 'sync_write_response' of module 'Memory' is unconnected for instance 'Data_Memory' [/eda/processor-ci-controller/src/controller.v:268]
WARNING: [Synth 8-7071] port 'sync_read_response' of module 'Memory' is unconnected for instance 'Data_Memory' [/eda/processor-ci-controller/src/controller.v:268]
WARNING: [Synth 8-7023] instance 'Data_Memory' of module 'Memory' has 11 connections declared, but only 8 given [/eda/processor-ci-controller/src/controller.v:268]
INFO: [Synth 8-6155] done synthesizing module 'Controller' (0#1) [/eda/processor-ci-controller/src/controller.v:1]
INFO: [Synth 8-6157] synthesizing module 'Core' [/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/core.v:2]
Parameter BOOT_ADDRESS bound to: 0 - type: integer
INFO: [Synth 8-6157] synthesizing module 'PC' [/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/pc.v:1]
INFO: [Synth 8-6155] done synthesizing module 'PC' (0#1) [/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/pc.v:1]
INFO: [Synth 8-6157] synthesizing module 'MUX' [/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mux.v:1]
INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mux.v:15]
INFO: [Synth 8-6155] done synthesizing module 'MUX' (0#1) [/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mux.v:1]
WARNING: [Synth 8-7071] port 'C' of module 'MUX' is unconnected for instance 'MemoryAddressMUX' [/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/core.v:84]
WARNING: [Synth 8-7071] port 'D' of module 'MUX' is unconnected for instance 'MemoryAddressMUX' [/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/core.v:84]
WARNING: [Synth 8-7071] port 'E' of module 'MUX' is unconnected for instance 'MemoryAddressMUX' [/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/core.v:84]
WARNING: [Synth 8-7071] port 'F' of module 'MUX' is unconnected for instance 'MemoryAddressMUX' [/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/core.v:84]
WARNING: [Synth 8-7071] port 'G' of module 'MUX' is unconnected for instance 'MemoryAddressMUX' [/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/core.v:84]
WARNING: [Synth 8-7071] port 'H' of module 'MUX' is unconnected for instance 'MemoryAddressMUX' [/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/core.v:84]
WARNING: [Synth 8-7023] instance 'MemoryAddressMUX' of module 'MUX' has 10 connections declared, but only 4 given [/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/core.v:84]
INFO: [Synth 8-6157] synthesizing module 'MDU' [/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:6]
INFO: [Synth 8-6155] done synthesizing module 'MDU' (0#1) [/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:6]
INFO: [Synth 8-6157] synthesizing module 'Registers' [/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:2]
INFO: [Synth 8-6155] done synthesizing module 'Registers' (0#1) [/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:2]
INFO: [Synth 8-6157] synthesizing module 'Control_Unit' [/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:2]
INFO: [Synth 8-155] case statement is not full and has no default [/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:171]
WARNING: [Synth 8-6090] variable 'mdu_start' is written by both blocking and non-blocking assignments, entire logic could be removed [/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:678]
INFO: [Synth 8-155] case statement is not full and has no default [/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:383]
INFO: [Synth 8-6155] done synthesizing module 'Control_Unit' (0#1) [/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:2]
INFO: [Synth 8-6157] synthesizing module 'ALU_Control' [/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/alu_control.v:1]
INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/alu_control.v:34]
INFO: [Synth 8-155] case statement is not full and has no default [/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/alu_control.v:11]
INFO: [Synth 8-6155] done synthesizing module 'ALU_Control' (0#1) [/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/alu_control.v:1]
INFO: [Synth 8-6157] synthesizing module 'Alu' [/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/alu.v:1]
INFO: [Synth 8-6155] done synthesizing module 'Alu' (0#1) [/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/alu.v:1]
INFO: [Synth 8-6157] synthesizing module 'Immediate_Generator' [/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/immediate_generator.v:1]
INFO: [Synth 8-6155] done synthesizing module 'Immediate_Generator' (0#1) [/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/immediate_generator.v:1]
INFO: [Synth 8-6157] synthesizing module 'CSR_Unit' [/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/csr_unit.v:3]
INFO: [Synth 8-155] case statement is not full and has no default [/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/csr_unit.v:119]
INFO: [Synth 8-6155] done synthesizing module 'CSR_Unit' (0#1) [/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/csr_unit.v:3]
INFO: [Synth 8-6155] done synthesizing module 'Core' (0#1) [/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/core.v:2]
WARNING: [Synth 8-7071] port 'halt' of module 'Core' is unconnected for instance 'Core' [/eda/processor_ci/rtl/Risco-5.v:92]
WARNING: [Synth 8-7071] port 'interruption_request_external' of module 'Core' is unconnected for instance 'Core' [/eda/processor_ci/rtl/Risco-5.v:92]
WARNING: [Synth 8-7071] port 'interruption_request_timer' of module 'Core' is unconnected for instance 'Core' [/eda/processor_ci/rtl/Risco-5.v:92]
WARNING: [Synth 8-7071] port 'interruption_request_software' of module 'Core' is unconnected for instance 'Core' [/eda/processor_ci/rtl/Risco-5.v:92]
WARNING: [Synth 8-7071] port 'interruption_request_fast' of module 'Core' is unconnected for instance 'Core' [/eda/processor_ci/rtl/Risco-5.v:92]
WARNING: [Synth 8-7023] instance 'Core' of module 'Core' has 14 connections declared, but only 9 given [/eda/processor_ci/rtl/Risco-5.v:92]
INFO: [Synth 8-6157] synthesizing module 'ResetBootSystem' [/eda/processor-ci-controller/src/reset.v:1]
Parameter CYCLES bound to: 20 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'ResetBootSystem' (0#1) [/eda/processor-ci-controller/src/reset.v:1]
WARNING: [Synth 8-7071] port 'start' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/eda/processor_ci/rtl/Risco-5.v:147]
WARNING: [Synth 8-7071] port 'resetn_o' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/eda/processor_ci/rtl/Risco-5.v:147]
WARNING: [Synth 8-7023] instance 'ResetBootSystem' of module 'ResetBootSystem' has 4 connections declared, but only 2 given [/eda/processor_ci/rtl/Risco-5.v:147]
INFO: [Synth 8-6155] done synthesizing module 'processorci_top' (0#1) [/eda/processor_ci/rtl/Risco-5.v:1]
WARNING: [Synth 8-3848] Net intr in module/entity Controller does not have driver. [/eda/processor-ci-controller/src/controller.v:25]
WARNING: [Synth 8-3848] Net temp_write_value in module/entity Core does not have driver. [/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/core.v:44]
WARNING: [Synth 8-3848] Net temp_address in module/entity Core does not have driver. [/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/core.v:43]
WARNING: [Synth 8-3848] Net memory_saved_value in module/entity Core does not have driver. [/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/core.v:43]
WARNING: [Synth 8-3848] Net alu_saved_value in module/entity Core does not have driver. [/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/core.v:44]
WARNING: [Synth 8-3848] Net miso in module/entity processorci_top does not have driver. [/eda/processor_ci/rtl/Risco-5.v:22]
WARNING: [Synth 8-7129] Port func3[2] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port func3[1] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port func3[0] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port csr_immediate[4] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port csr_immediate[3] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port csr_immediate[2] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port csr_immediate[1] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port csr_immediate[0] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port interruption_request_external in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port interruption_request_timer in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port interruption_request_software in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port interruption_request_fast[15] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port interruption_request_fast[14] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port interruption_request_fast[13] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port interruption_request_fast[12] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port interruption_request_fast[11] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port interruption_request_fast[10] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port interruption_request_fast[9] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port interruption_request_fast[8] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port interruption_request_fast[7] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port interruption_request_fast[6] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port interruption_request_fast[5] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port interruption_request_fast[4] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port interruption_request_fast[3] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port interruption_request_fast[2] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port interruption_request_fast[1] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port interruption_request_fast[0] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port pc_value[31] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port pc_value[30] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port pc_value[29] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port pc_value[28] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port pc_value[27] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port pc_value[26] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port pc_value[25] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port pc_value[24] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port pc_value[23] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port pc_value[22] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port pc_value[21] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port pc_value[20] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port pc_value[19] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port pc_value[18] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port pc_value[17] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port pc_value[16] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port pc_value[15] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port pc_value[14] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port pc_value[13] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port pc_value[12] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port pc_value[11] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port pc_value[10] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port pc_value[9] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port pc_value[8] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port pc_value[7] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port pc_value[6] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port pc_value[5] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port pc_value[4] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port pc_value[3] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port pc_value[2] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port pc_value[1] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port pc_value[0] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port func7[6] in module ALU_Control is either unconnected or has no load
WARNING: [Synth 8-7129] Port func7[4] in module ALU_Control is either unconnected or has no load
WARNING: [Synth 8-7129] Port func7[3] in module ALU_Control is either unconnected or has no load
WARNING: [Synth 8-7129] Port func7[2] in module ALU_Control is either unconnected or has no load
WARNING: [Synth 8-7129] Port func7[1] in module ALU_Control is either unconnected or has no load
WARNING: [Synth 8-7129] Port func7[0] in module ALU_Control is either unconnected or has no load
WARNING: [Synth 8-7129] Port halt in module Core is either unconnected or has no load
WARNING: [Synth 8-7129] Port reset in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[31] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[30] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[29] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[28] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[27] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[26] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[25] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[24] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[23] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[22] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[21] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[20] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[19] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[18] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[17] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[16] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[15] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[14] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[13] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[12] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[1] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[0] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port communication_tx_empty in module Interpreter is either unconnected or has no load
WARNING: [Synth 8-7129] Port memory_response in module Interpreter is either unconnected or has no load
WARNING: [Synth 8-7129] Port intr in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port sck in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port cs in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port mosi in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port miso in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port rw in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port reset in module processorci_top is either unconnected or has no load
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2128.750 ; gain = 500.598 ; free physical = 225 ; free virtual = 24927
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2146.562 ; gain = 518.410 ; free physical = 214 ; free virtual = 24916
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2146.562 ; gain = 518.410 ; free physical = 214 ; free virtual = 24916
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2146.562 ; gain = 0.000 ; free physical = 212 ; free virtual = 24914
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]
WARNING: [Vivado 12-507] No nets matched 'sck_IBUF'. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
Finished Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/processorci_top_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/processorci_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2297.344 ; gain = 0.000 ; free physical = 273 ; free virtual = 24992
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2297.379 ; gain = 0.000 ; free physical = 253 ; free virtual = 24973
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:35 ; elapsed = 00:00:35 . Memory (MB): peak = 2297.379 ; gain = 669.227 ; free physical = 172 ; free virtual = 24849
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7a100tcsg324-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:35 ; elapsed = 00:00:35 . Memory (MB): peak = 2297.379 ; gain = 669.227 ; free physical = 172 ; free virtual = 24849
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:35 ; elapsed = 00:00:35 . Memory (MB): peak = 2297.379 ; gain = 669.227 ; free physical = 172 ; free virtual = 24849
---------------------------------------------------------------------------------
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_rx'
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tx'
INFO: [Synth 8-802] inferred FSM for state register 'state_read_reg' in module 'UART'
INFO: [Synth 8-802] inferred FSM for state register 'state_write_reg' in module 'UART'
INFO: [Synth 8-802] inferred FSM for state register 'tx_fifo_read_state_reg' in module 'UART'
INFO: [Synth 8-802] inferred FSM for state register 'state_mul_reg' in module 'MDU'
INFO: [Synth 8-802] inferred FSM for state register 'state_div_reg' in module 'MDU'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'Control_Unit'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'ResetBootSystem'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FSM_IDLE | 00 | 000
FSM_START | 11 | 001
FSM_RECV | 10 | 010
FSM_STOP | 01 | 011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_rx'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FSM_IDLE | 00 | 000
FSM_START | 11 | 001
FSM_SEND | 10 | 010
FSM_STOP | 01 | 011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tx'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
IDLE | 000 | 0000
READ | 001 | 0001
COPY_READ_BUFFER | 010 | 0100
WB | 011 | 0010
FINISH | 100 | 0011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_read_reg' using encoding 'sequential' in module 'UART'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
IDLE | 000 | 0000
COPY_WRITE_BUFFER | 001 | 0100
WRITE | 010 | 0001
WB | 011 | 0010
FINISH | 100 | 0011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_write_reg' using encoding 'sequential' in module 'UART'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
iSTATE | 0001 | 00
iSTATE0 | 0010 | 01
iSTATE1 | 0100 | 10
iSTATE2 | 1000 | 11
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'tx_fifo_read_state_reg' using encoding 'one-hot' in module 'UART'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
IDLE | 001 | 00
OPERATE | 010 | 01
FINISH | 100 | 10
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_mul_reg' using encoding 'one-hot' in module 'MDU'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FETCH | 00000000000000000000000000000000000000000000000001 | 000000
VALIDATE_FETCH | 00000000000000000000000000000000000000000000000010 | 101110
DECODE | 00000000000000000000000000000000000000000000000100 | 000001
MEMADR | 00000000000000000000000000000000000000000000001000 | 000010
MEMREAD_UNALIGNED | 00000000000000000000000000000000000000000000010000 | 010110
LOAD_FIRST_BLOCK | 00000000000000000000000000000000000000000000100000 | 010000
SAVE_FIRST_BLOCK | 00000000000000000000000000000000000000000001000000 | 010001
CALC_NEXT_ADDRESS | 00000000000000000000000000000000000000000010000000 | 010010
READ_SECOND_BLOCK | 00000000000000000000000000000000000000000100000000 | 010011
LOAD_SECOND_BLOCK | 00000000000000000000000000000000000000001000000000 | 010100
MERGE_BLOCKS | 00000000000000000000000000000000000000010000000000 | 010101
FILTER_ALU_WB | 00000000000000000000000000000000000000100000000000 | 010111
MEMREAD | 00000000000000000000000000000000000001000000000000 | 000011
MEMWB | 00000000000000000000000000000000000010000000000000 | 000100
MEMWRITE_UNALIGNED | 00000000000000000000000000000000000100000000000000 | 011000
GEN_FIRST_BLOCK_PART_1 | 00000000000000000000000000000000001000000000000000 | 011001
GEN_FIRST_BLOCK_PART_2 | 00000000000000000000000000000000010000000000000000 | 011010
GEN_SECOND_BLOCK_PART_1 | 00000000000000000000000000000000100000000000000000 | 011011
GEN_SECOND_BLOCK_PART_2 | 00000000000000000000000000000001000000000000000000 | 011100
MERGE_WRITE_BLOCKS | 00000000000000000000000000000010000000000000000000 | 011101
SWAP_VALUE_DIRECTION | 00000000000000000000000000000100000000000000000000 | 011110
CLEAR_VALUE_HALF_BYTE_ONE_BLOCK | 00000000000000000000000000001000000000000000000000 | 100010
CLEAR_VALUE_HALF_BYTE_ONE_BLOCK_2 | 00000000000000000000000000010000000000000000000000 | 100011
CLEAR_VALUE_HALF_BYTE_ONE_BLOCK_3 | 00000000000000000000000000100000000000000000000000 | 100100
CLEAR_VALUE | 00000000000000000000000001000000000000000000000000 | 011111
MERGE_WRITE_VALUE_1 | 00000000000000000000000010000000000000000000000000 | 100000
WRITE_VALUE_1 | 00000000000000000000000100000000000000000000000000 | 100001
CALC_SECOND_BLOCK_ADDRESS_TO_WRITE | 00000000000000000000001000000000000000000000000000 | 100101
READ_SECOND_BLOCK_TO_WRITE | 00000000000000000000010000000000000000000000000000 | 100110
LOAD_SECOND_BLOCK_TO_WRITE | 00000000000000000000100000000000000000000000000000 | 100111
LOAD_SECOND_BLOCK_TO_WRITE_2 | 00000000000000000001000000000000000000000000000000 | 101000
SWAP_VALUE_DIRECTION_2 | 00000000000000000010000000000000000000000000000000 | 101001
CLEAR_VALUE_PART_2 | 00000000000000000100000000000000000000000000000000 | 101010
CLEAR_VALUE_PART_2_1 | 00000000000000001000000000000000000000000000000000 | 101011
MERGE_WRITE_VALUE_2 | 00000000000000010000000000000000000000000000000000 | 101100
WRITE_VALUE_2 | 00000000000000100000000000000000000000000000000000 | 101101
MEMWRITE | 00000000000001000000000000000000000000000000000000 | 000101
EXECUTER | 00000000000010000000000000000000000000000000000000 | 000110
EXECUTE_MDU | 00000000000100000000000000000000000000000000000000 | 101111
MDU_WAIT | 00000000001000000000000000000000000000000000000000 | 110000
MDU_WB | 00000000010000000000000000000000000000000000000000 | 110001
EXECUTEI | 00000000100000000000000000000000000000000000000000 | 001000
JAL | 00000001000000000000000000000000000000000000000000 | 001001
BRANCH | 00000010000000000000000000000000000000000000000000 | 001010
AUIPC | 00000100000000000000000000000000000000000000000000 | 001100
LUI | 00001000000000000000000000000000000000000000000000 | 001101
JALR_PC | 00010000000000000000000000000000000000000000000000 | 001110
JALR | 00100000000000000000000000000000000000000000000000 | 001011
ALUWB | 01000000000000000000000000000000000000000000000000 | 000111
EXECUTECSR | 10000000000000000000000000000000000000000000000000 | 001111
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'Control_Unit'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
RESET_COUNTER | 00 | 01
IDLE | 01 | 10
INIT | 10 | 00
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'ResetBootSystem'
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2297.379 ; gain = 669.227 ; free physical = 154 ; free virtual = 24832
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 64 Bit Adders := 2
2 Input 32 Bit Adders := 11
3 Input 32 Bit Adders := 2
2 Input 24 Bit Adders := 2
2 Input 10 Bit Adders := 2
2 Input 8 Bit Adders := 1
2 Input 6 Bit Adders := 4
2 Input 5 Bit Adders := 1
2 Input 4 Bit Adders := 2
2 Input 3 Bit Adders := 3
2 Input 2 Bit Adders := 1
+---XORs :
2 Input 32 Bit XORs := 1
+---XORs :
2 Bit Wide XORs := 1
+---Registers :
64 Bit Registers := 6
32 Bit Registers := 65
24 Bit Registers := 5
10 Bit Registers := 2
8 Bit Registers := 11
6 Bit Registers := 1
4 Bit Registers := 2
3 Bit Registers := 2
1 Bit Registers := 31
+---Multipliers :
32x32 Multipliers := 1
+---RAMs :
32K Bit (1024 X 32 bit) RAMs := 2
64 Bit (8 X 8 bit) RAMs := 2
+---Muxes :
4 Input 64 Bit Muxes := 3
2 Input 64 Bit Muxes := 1
48 Input 64 Bit Muxes := 2
50 Input 50 Bit Muxes := 1
2 Input 50 Bit Muxes := 19
11 Input 50 Bit Muxes := 1
2 Input 32 Bit Muxes := 22
5 Input 32 Bit Muxes := 1
4 Input 32 Bit Muxes := 3
8 Input 32 Bit Muxes := 1
15 Input 32 Bit Muxes := 1
48 Input 24 Bit Muxes := 1
48 Input 8 Bit Muxes := 2
2 Input 8 Bit Muxes := 4
24 Input 7 Bit Muxes := 1
2 Input 7 Bit Muxes := 2
2 Input 6 Bit Muxes := 4
3 Input 6 Bit Muxes := 1
2 Input 5 Bit Muxes := 2
2 Input 4 Bit Muxes := 5
50 Input 4 Bit Muxes := 1
9 Input 4 Bit Muxes := 1
10 Input 4 Bit Muxes := 1
23 Input 4 Bit Muxes := 1
5 Input 3 Bit Muxes := 5
2 Input 3 Bit Muxes := 7
3 Input 3 Bit Muxes := 1
4 Input 3 Bit Muxes := 2
50 Input 3 Bit Muxes := 3
10 Input 3 Bit Muxes := 1
2 Input 2 Bit Muxes := 17
48 Input 2 Bit Muxes := 1
4 Input 2 Bit Muxes := 5
50 Input 2 Bit Muxes := 2
3 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 89
48 Input 1 Bit Muxes := 22
3 Input 1 Bit Muxes := 7
4 Input 1 Bit Muxes := 7
5 Input 1 Bit Muxes := 11
50 Input 1 Bit Muxes := 12
6 Input 1 Bit Muxes := 5
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 240 (col length:80)
BRAMs: 270 (col length: RAMB18 80 RAMB36 40)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
DSP Report: Generating DSP acumulador0, operation Mode is: A2*B.
DSP Report: register acumulador0 is absorbed into DSP acumulador0.
DSP Report: operator acumulador0 is absorbed into DSP acumulador0.
DSP Report: operator acumulador0 is absorbed into DSP acumulador0.
DSP Report: Generating DSP acumulador_reg, operation Mode is: (PCIN>>17)+A*B.
DSP Report: register acumulador_reg is absorbed into DSP acumulador_reg.
DSP Report: operator acumulador0 is absorbed into DSP acumulador_reg.
DSP Report: operator acumulador0 is absorbed into DSP acumulador_reg.
DSP Report: Generating DSP acumulador0, operation Mode is: A2*B2.
DSP Report: register acumulador0 is absorbed into DSP acumulador0.
DSP Report: register acumulador0 is absorbed into DSP acumulador0.
DSP Report: operator acumulador0 is absorbed into DSP acumulador0.
DSP Report: operator acumulador0 is absorbed into DSP acumulador0.
DSP Report: Generating DSP acumulador_reg, operation Mode is: (PCIN>>17)+A2*B.
DSP Report: register acumulador_reg is absorbed into DSP acumulador_reg.
DSP Report: register acumulador_reg is absorbed into DSP acumulador_reg.
DSP Report: operator acumulador0 is absorbed into DSP acumulador_reg.
DSP Report: operator acumulador0 is absorbed into DSP acumulador_reg.
WARNING: [Synth 8-7129] Port func3[2] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port func3[1] in module CSR_Unit is either unconnected or has no load
INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[47]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[46]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[45]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[44]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[43]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[42]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[41]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[40]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[39]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[38]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[37]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[36]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[35]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[34]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[33]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[32]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[31]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[30]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[29]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[28]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[27]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[26]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[25]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[24]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[23]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[22]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[21]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[20]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[19]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[18]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[17]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[47]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[46]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[45]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[44]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[43]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[42]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[41]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[40]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[39]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[38]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[37]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[36]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[35]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[34]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[33]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[32]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[31]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[30]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[29]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[28]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[27]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[26]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[25]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[24]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[23]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[22]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[21]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[20]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[19]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[18]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[17]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (FSM_onehot_state_reg[22]) is unused and will be removed from module Control_Unit.
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:27 ; elapsed = 00:01:28 . Memory (MB): peak = 2297.379 ; gain = 669.227 ; free physical = 167 ; free virtual = 24688
---------------------------------------------------------------------------------
Sort Area is acumulador0_3 : 0 0 : 2737 4966 : Used 1 time 0
Sort Area is acumulador0_3 : 0 1 : 2229 4966 : Used 1 time 0
Sort Area is acumulador0_0 : 0 0 : 2176 4080 : Used 1 time 0
Sort Area is acumulador0_0 : 0 1 : 1904 4080 : Used 1 time 0
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
ROM: Preliminary Mapping Report
+------------+---------------------+---------------+----------------+
|Module Name | RTL Object | Depth x Width | Implemented As |
+------------+---------------------+---------------+----------------+
|Interpreter | memory_mux_selector | 256x1 | LUT |
|Interpreter | memory_mux_selector | 256x1 | LUT |
+------------+---------------------+---------------+----------------+
Distributed RAM: Preliminary Mapping Report (see note below)
+----------------+------------------------------------+-----------+----------------------+------------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+----------------+------------------------------------+-----------+----------------------+------------------+
|processorci_top | Controller/Uart/TX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
|processorci_top | Controller/Uart/RX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
|processorci_top | Controller/Memory/memory_reg | Implied | 1 K x 32 | RAM256X1S x 128 |
|processorci_top | Controller/Data_Memory/memory_reg | Implied | 1 K x 32 | RAM256X1S x 128 |
+----------------+------------------------------------+-----------+----------------------+------------------+
Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
DSP: Preliminary Mapping Report (see note below. The ' indicates corresponding REG is set)
+------------+-----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG |
+------------+-----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|MDU | A2*B | 18 | 15 | - | - | 48 | 1 | 0 | - | - | - | 0 | 0 |
|MDU | (PCIN>>17)+A*B | 15 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
|MDU | A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
|MDU | (PCIN>>17)+A2*B | 18 | 15 | - | - | 48 | 1 | 0 | - | - | - | 0 | 1 |
+------------+-----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:42 ; elapsed = 00:01:43 . Memory (MB): peak = 2297.379 ; gain = 669.227 ; free physical = 166 ; free virtual = 24687
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:02:05 ; elapsed = 00:02:06 . Memory (MB): peak = 2297.379 ; gain = 669.227 ; free physical = 161 ; free virtual = 24650
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Distributed RAM: Final Mapping Report
+----------------+------------------------------------+-----------+----------------------+------------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+----------------+------------------------------------+-----------+----------------------+------------------+
|processorci_top | Controller/Uart/TX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
|processorci_top | Controller/Uart/RX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
|processorci_top | Controller/Memory/memory_reg | Implied | 1 K x 32 | RAM256X1S x 128 |
|processorci_top | Controller/Data_Memory/memory_reg | Implied | 1 K x 32 | RAM256X1S x 128 |
+----------------+------------------------------------+-----------+----------------------+------------------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:02:14 ; elapsed = 00:02:15 . Memory (MB): peak = 2297.379 ; gain = 669.227 ; free physical = 167 ; free virtual = 24651
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:02:23 ; elapsed = 00:02:24 . Memory (MB): peak = 2297.379 ; gain = 669.227 ; free physical = 176 ; free virtual = 24660
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:02:23 ; elapsed = 00:02:24 . Memory (MB): peak = 2297.379 ; gain = 669.227 ; free physical = 176 ; free virtual = 24660
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:02:25 ; elapsed = 00:02:27 . Memory (MB): peak = 2297.379 ; gain = 669.227 ; free physical = 168 ; free virtual = 24652
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:02:25 ; elapsed = 00:02:27 . Memory (MB): peak = 2297.379 ; gain = 669.227 ; free physical = 168 ; free virtual = 24652
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:02:26 ; elapsed = 00:02:27 . Memory (MB): peak = 2297.379 ; gain = 669.227 ; free physical = 168 ; free virtual = 24652
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:02:26 ; elapsed = 00:02:27 . Memory (MB): peak = 2297.379 ; gain = 669.227 ; free physical = 168 ; free virtual = 24652
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
DSP Final Report (the ' indicates corresponding REG is set)
+------------+---------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG |
+------------+---------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|MDU | A''*B'' | 17 | 18 | - | - | 48 | 2 | 2 | - | - | - | 0 | 0 |
|MDU | (PCIN>>17+A''*B'')' | 30 | 18 | - | - | 48 | 2 | 2 | - | - | - | 0 | 1 |
|MDU | A''*B'' | 17 | 17 | - | - | 48 | 2 | 2 | - | - | - | 0 | 0 |
|MDU | (PCIN>>17+A''*B'')' | 17 | 18 | - | - | 48 | 2 | 2 | - | - | - | 0 | 1 |
+------------+---------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+----------+------+
| |Cell |Count |
+------+----------+------+
|1 |BUFG | 2|
|2 |CARRY4 | 176|
|3 |DSP48E1 | 4|
|5 |LUT1 | 172|
|6 |LUT2 | 456|
|7 |LUT3 | 440|
|8 |LUT4 | 248|
|9 |LUT5 | 399|
|10 |LUT6 | 1831|
|11 |MUXF7 | 459|
|12 |MUXF8 | 1|
|13 |RAM256X1S | 256|
|14 |RAM32M | 2|
|15 |RAM32X1D | 4|
|16 |FDRE | 2546|
|17 |FDSE | 7|
|18 |IBUF | 2|
|19 |OBUF | 1|
|20 |OBUFT | 2|
+------+----------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:02:26 ; elapsed = 00:02:27 . Memory (MB): peak = 2297.379 ; gain = 669.227 ; free physical = 168 ; free virtual = 24652
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 156 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:02:21 ; elapsed = 00:02:22 . Memory (MB): peak = 2297.379 ; gain = 518.410 ; free physical = 168 ; free virtual = 24652
Synthesis Optimization Complete : Time (s): cpu = 00:02:26 ; elapsed = 00:02:28 . Memory (MB): peak = 2297.379 ; gain = 669.227 ; free physical = 168 ; free virtual = 24652
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2297.379 ; gain = 0.000 ; free physical = 447 ; free virtual = 24930
INFO: [Netlist 29-17] Analyzing 902 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]
WARNING: [Vivado 12-507] No nets matched 'sck_IBUF'. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
Finished Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2369.375 ; gain = 0.000 ; free physical = 449 ; free virtual = 24933
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 262 instances were transformed.
RAM256X1S => RAM256X1S (MUXF7(x2), MUXF8, RAMS64E(x4)): 256 instances
RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 2 instances
RAM32X1D => RAM32X1D (RAMD32(x2)): 4 instances
Synth Design complete | Checksum: 2ec83021
INFO: [Common 17-83] Releasing license: Synthesis
82 Infos, 201 Warnings, 2 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:02:45 ; elapsed = 00:02:41 . Memory (MB): peak = 2369.410 ; gain = 1061.297 ; free physical = 450 ; free virtual = 24934
INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2081.131; main = 1788.619; forked = 433.069
INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3254.777; main = 2369.379; forked = 981.445
# opt_design
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command opt_design
Starting DRC Task
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2433.406 ; gain = 63.996 ; free physical = 452 ; free virtual = 24936
Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: fd9f535c
Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 2489.195 ; gain = 55.789 ; free physical = 408 ; free virtual = 24892
Starting Logic Optimization Task
Phase 1 Initialization
Phase 1.1 Core Generation And Design Setup
Phase 1.1 Core Generation And Design Setup | Checksum: fd9f535c
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2736.164 ; gain = 0.000 ; free physical = 162 ; free virtual = 24625
Phase 1.2 Setup Constraints And Sort Netlist
Phase 1.2 Setup Constraints And Sort Netlist | Checksum: fd9f535c
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2736.164 ; gain = 0.000 ; free physical = 161 ; free virtual = 24625
Phase 1 Initialization | Checksum: fd9f535c
Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2736.164 ; gain = 0.000 ; free physical = 161 ; free virtual = 24624
Phase 2 Timer Update And Timing Data Collection
Phase 2.1 Timer Update
Phase 2.1 Timer Update | Checksum: fd9f535c
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.61 . Memory (MB): peak = 2736.164 ; gain = 0.000 ; free physical = 161 ; free virtual = 24624
Phase 2.2 Timing Data Collection
Phase 2.2 Timing Data Collection | Checksum: fd9f535c
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.64 . Memory (MB): peak = 2736.164 ; gain = 0.000 ; free physical = 159 ; free virtual = 24622
Phase 2 Timer Update And Timing Data Collection | Checksum: fd9f535c
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.65 . Memory (MB): peak = 2736.164 ; gain = 0.000 ; free physical = 158 ; free virtual = 24622
Phase 3 Retarget
INFO: [Opt 31-1566] Pulled 6 inverters resulting in an inversion of 18 pins
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 3 Retarget | Checksum: 112c910ac
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.96 . Memory (MB): peak = 2736.164 ; gain = 0.000 ; free physical = 165 ; free virtual = 24628
Retarget | Checksum: 112c910ac
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 6 cells
Phase 4 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 4 Constant propagation | Checksum: 1c136aa80
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2736.164 ; gain = 0.000 ; free physical = 165 ; free virtual = 24628
Constant propagation | Checksum: 1c136aa80
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 5 Sweep
Phase 5 Sweep | Checksum: 1a25ec48d
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2736.164 ; gain = 0.000 ; free physical = 165 ; free virtual = 24628
Sweep | Checksum: 1a25ec48d
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
Phase 6 BUFG optimization
Phase 6 BUFG optimization | Checksum: 1a25ec48d
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2768.180 ; gain = 32.016 ; free physical = 165 ; free virtual = 24628
BUFG optimization | Checksum: 1a25ec48d
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
Phase 7 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 7 Shift Register Optimization | Checksum: 1a25ec48d
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2768.180 ; gain = 32.016 ; free physical = 165 ; free virtual = 24628
Shift Register Optimization | Checksum: 1a25ec48d
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 8 Post Processing Netlist
Phase 8 Post Processing Netlist | Checksum: 1a25ec48d
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2768.180 ; gain = 32.016 ; free physical = 165 ; free virtual = 24628
Post Processing Netlist | Checksum: 1a25ec48d
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Phase 9 Finalization
Phase 9.1 Finalizing Design Cores and Updating Shapes
Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 130f4a278
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2768.180 ; gain = 32.016 ; free physical = 165 ; free virtual = 24628
Phase 9.2 Verifying Netlist Connectivity
Starting Connectivity Check Task
Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2768.180 ; gain = 0.000 ; free physical = 165 ; free virtual = 24628
Phase 9.2 Verifying Netlist Connectivity | Checksum: 130f4a278
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2768.180 ; gain = 32.016 ; free physical = 165 ; free virtual = 24628
Phase 9 Finalization | Checksum: 130f4a278
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2768.180 ; gain = 32.016 ; free physical = 165 ; free virtual = 24628
Opt_design Change Summary
=========================
-------------------------------------------------------------------------------------------------------------------------
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
-------------------------------------------------------------------------------------------------------------------------
| Retarget | 0 | 6 | 0 |
| Constant propagation | 0 | 0 | 0 |
| Sweep | 0 | 0 | 0 |
| BUFG optimization | 0 | 0 | 0 |
| Shift Register Optimization | 0 | 0 | 0 |
| Post Processing Netlist | 0 | 0 | 0 |
-------------------------------------------------------------------------------------------------------------------------
Ending Logic Optimization Task | Checksum: 130f4a278
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2768.180 ; gain = 32.016 ; free physical = 165 ; free virtual = 24628
INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2768.180 ; gain = 0.000 ; free physical = 165 ; free virtual = 24628
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 130f4a278
Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2768.180 ; gain = 0.000 ; free physical = 165 ; free virtual = 24628
Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 130f4a278
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2768.180 ; gain = 0.000 ; free physical = 165 ; free virtual = 24628
Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2768.180 ; gain = 0.000 ; free physical = 165 ; free virtual = 24628
Ending Netlist Obfuscation Task | Checksum: 130f4a278
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2768.180 ; gain = 0.000 ; free physical = 165 ; free virtual = 24628
INFO: [Common 17-83] Releasing license: Implementation
19 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:17 ; elapsed = 00:00:15 . Memory (MB): peak = 2768.180 ; gain = 398.770 ; free physical = 165 ; free virtual = 24628
# place_design
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-83] Releasing license: Implementation
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs
Starting Placer Task
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2800.195 ; gain = 0.000 ; free physical = 169 ; free virtual = 24626
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a7777071
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2800.195 ; gain = 0.000 ; free physical = 169 ; free virtual = 24626
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2800.195 ; gain = 0.000 ; free physical = 169 ; free virtual = 24626
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 149e21c91
Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 2800.195 ; gain = 0.000 ; free physical = 170 ; free virtual = 24627
Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 159a91c94
Time (s): cpu = 00:00:12 ; elapsed = 00:00:08 . Memory (MB): peak = 2807.223 ; gain = 7.027 ; free physical = 168 ; free virtual = 24620
Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 159a91c94
Time (s): cpu = 00:00:12 ; elapsed = 00:00:08 . Memory (MB): peak = 2807.223 ; gain = 7.027 ; free physical = 166 ; free virtual = 24617
Phase 1 Placer Initialization | Checksum: 159a91c94
Time (s): cpu = 00:00:12 ; elapsed = 00:00:08 . Memory (MB): peak = 2807.223 ; gain = 7.027 ; free physical = 163 ; free virtual = 24614
Phase 2 Global Placement
Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 18ff24549
Time (s): cpu = 00:00:16 ; elapsed = 00:00:09 . Memory (MB): peak = 2807.223 ; gain = 7.027 ; free physical = 172 ; free virtual = 24624
Phase 2.2 Update Timing before SLR Path Opt
Phase 2.2 Update Timing before SLR Path Opt | Checksum: 17adfa402
Time (s): cpu = 00:00:19 ; elapsed = 00:00:10 . Memory (MB): peak = 2807.223 ; gain = 7.027 ; free physical = 167 ; free virtual = 24619
Phase 2.3 Post-Processing in Floorplanning
Phase 2.3 Post-Processing in Floorplanning | Checksum: 17adfa402
Time (s): cpu = 00:00:19 ; elapsed = 00:00:11 . Memory (MB): peak = 2807.223 ; gain = 7.027 ; free physical = 163 ; free virtual = 24615
Phase 2.4 Global Placement Core
Phase 2.4.1 UpdateTiming Before Physical Synthesis
Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 134f72ef9
Time (s): cpu = 00:01:00 ; elapsed = 00:00:31 . Memory (MB): peak = 2807.223 ; gain = 7.027 ; free physical = 168 ; free virtual = 24615
Phase 2.4.2 Physical Synthesis In Placer
INFO: [Physopt 32-1035] Found 64 LUTNM shape to break, 137 LUT instances to create LUTNM shape
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 5, two critical 59, total 64, new lutff created 0
INFO: [Physopt 32-1138] End 1 Pass. Optimized 122 nets or LUTs. Breaked 64 LUTs, combined 58 existing LUTs and moved 0 existing LUT
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design.
INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization
INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-1401] No candidate cells found for Shift Register optimization.
INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2807.223 ; gain = 0.000 ; free physical = 172 ; free virtual = 24619
Summary of Physical Synthesis Optimizations
============================================
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| LUT Combining | 64 | 58 | 122 | 0 | 1 | 00:00:01 |
| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| BRAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| URAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Total | 64 | 58 | 122 | 0 | 9 | 00:00:01 |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
Phase 2.4.2 Physical Synthesis In Placer | Checksum: 82efd306
Time (s): cpu = 00:01:05 ; elapsed = 00:00:34 . Memory (MB): peak = 2807.223 ; gain = 7.027 ; free physical = 167 ; free virtual = 24615
Phase 2.4 Global Placement Core | Checksum: 1573edd13
Time (s): cpu = 00:01:25 ; elapsed = 00:00:42 . Memory (MB): peak = 2807.223 ; gain = 7.027 ; free physical = 171 ; free virtual = 24619
Phase 2 Global Placement | Checksum: 1573edd13
Time (s): cpu = 00:01:25 ; elapsed = 00:00:42 . Memory (MB): peak = 2807.223 ; gain = 7.027 ; free physical = 171 ; free virtual = 24619
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 14cfe0e11
Time (s): cpu = 00:01:28 ; elapsed = 00:00:43 . Memory (MB): peak = 2807.223 ; gain = 7.027 ; free physical = 172 ; free virtual = 24619
Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 17503a6c1
Time (s): cpu = 00:01:35 ; elapsed = 00:00:47 . Memory (MB): peak = 2807.223 ; gain = 7.027 ; free physical = 158 ; free virtual = 24606
Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 18167845c
Time (s): cpu = 00:01:35 ; elapsed = 00:00:47 . Memory (MB): peak = 2807.223 ; gain = 7.027 ; free physical = 170 ; free virtual = 24617
Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 19c3bf2e9
Time (s): cpu = 00:01:35 ; elapsed = 00:00:47 . Memory (MB): peak = 2807.223 ; gain = 7.027 ; free physical = 166 ; free virtual = 24613
Phase 3.5 Fast Optimization
Phase 3.5 Fast Optimization | Checksum: 2081cf2c6
Time (s): cpu = 00:01:49 ; elapsed = 00:00:57 . Memory (MB): peak = 2807.223 ; gain = 7.027 ; free physical = 271 ; free virtual = 24603
Phase 3.6 Small Shape Detail Placement
Phase 3.6 Small Shape Detail Placement | Checksum: 1b01f32a1
Time (s): cpu = 00:01:55 ; elapsed = 00:01:03 . Memory (MB): peak = 2807.223 ; gain = 7.027 ; free physical = 278 ; free virtual = 24609
Phase 3.7 Re-assign LUT pins
Phase 3.7 Re-assign LUT pins | Checksum: 187f8f9b8
Time (s): cpu = 00:01:56 ; elapsed = 00:01:04 . Memory (MB): peak = 2807.223 ; gain = 7.027 ; free physical = 269 ; free virtual = 24600
Phase 3.8 Pipeline Register Optimization
Phase 3.8 Pipeline Register Optimization | Checksum: 11d7c136c
Time (s): cpu = 00:01:56 ; elapsed = 00:01:04 . Memory (MB): peak = 2807.223 ; gain = 7.027 ; free physical = 267 ; free virtual = 24599
Phase 3.9 Fast Optimization
Phase 3.9 Fast Optimization | Checksum: da6b0ecc
Time (s): cpu = 00:02:27 ; elapsed = 00:01:30 . Memory (MB): peak = 2807.223 ; gain = 7.027 ; free physical = 263 ; free virtual = 24595
Phase 3 Detail Placement | Checksum: da6b0ecc
Time (s): cpu = 00:02:28 ; elapsed = 00:01:30 . Memory (MB): peak = 2807.223 ; gain = 7.027 ; free physical = 263 ; free virtual = 24595
Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 11b538aa4
Phase 4.1.1.1 BUFG Insertion
Starting Physical Synthesis Task
Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.888 | TNS=-317.331 |
Phase 1 Physical Synthesis Initialization | Checksum: 11ae5226d
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2807.223 ; gain = 0.000 ; free physical = 261 ; free virtual = 24594
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
Ending Physical Synthesis Task | Checksum: 11ae5226d
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2807.223 ; gain = 0.000 ; free physical = 261 ; free virtual = 24594
Phase 4.1.1.1 BUFG Insertion | Checksum: 11b538aa4
Time (s): cpu = 00:02:39 ; elapsed = 00:01:36 . Memory (MB): peak = 2807.223 ; gain = 7.027 ; free physical = 261 ; free virtual = 24594
Phase 4.1.1.2 Post Placement Timing Optimization
INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.800. For the most accurate timing information please run report_timing.
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: aafaf2ee
Time (s): cpu = 00:04:44 ; elapsed = 00:03:40 . Memory (MB): peak = 2807.223 ; gain = 7.027 ; free physical = 257 ; free virtual = 24589
Time (s): cpu = 00:04:44 ; elapsed = 00:03:40 . Memory (MB): peak = 2807.223 ; gain = 7.027 ; free physical = 257 ; free virtual = 24589
Phase 4.1 Post Commit Optimization | Checksum: aafaf2ee
Time (s): cpu = 00:04:44 ; elapsed = 00:03:40 . Memory (MB): peak = 2807.223 ; gain = 7.027 ; free physical = 257 ; free virtual = 24589
Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: aafaf2ee
Time (s): cpu = 00:04:44 ; elapsed = 00:03:41 . Memory (MB): peak = 2807.223 ; gain = 7.027 ; free physical = 257 ; free virtual = 24589
Phase 4.3 Placer Reporting
Phase 4.3.1 Print Estimated Congestion
INFO: [Place 30-612] Post-Placement Estimated Congestion
____________________________________________________
| | Global Congestion | Short Congestion |
| Direction | Region Size | Region Size |
|___________|___________________|___________________|
| North| 1x1| 2x2|
|___________|___________________|___________________|
| South| 1x1| 4x4|
|___________|___________________|___________________|
| East| 2x2| 2x2|
|___________|___________________|___________________|
| West| 1x1| 2x2|
|___________|___________________|___________________|
Phase 4.3.1 Print Estimated Congestion | Checksum: aafaf2ee
Time (s): cpu = 00:04:44 ; elapsed = 00:03:41 . Memory (MB): peak = 2807.223 ; gain = 7.027 ; free physical = 257 ; free virtual = 24589
Phase 4.3 Placer Reporting | Checksum: aafaf2ee
Time (s): cpu = 00:04:44 ; elapsed = 00:03:41 . Memory (MB): peak = 2807.223 ; gain = 7.027 ; free physical = 257 ; free virtual = 24589
Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2807.223 ; gain = 0.000 ; free physical = 257 ; free virtual = 24589
Time (s): cpu = 00:04:44 ; elapsed = 00:03:41 . Memory (MB): peak = 2807.223 ; gain = 7.027 ; free physical = 257 ; free virtual = 24589
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 776ca5e4
Time (s): cpu = 00:04:44 ; elapsed = 00:03:41 . Memory (MB): peak = 2807.223 ; gain = 7.027 ; free physical = 256 ; free virtual = 24589
Ending Placer Task | Checksum: 4b50201c
Time (s): cpu = 00:04:44 ; elapsed = 00:03:41 . Memory (MB): peak = 2807.223 ; gain = 7.027 ; free physical = 264 ; free virtual = 24596
37 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:04:47 ; elapsed = 00:03:42 . Memory (MB): peak = 2807.223 ; gain = 39.043 ; free physical = 264 ; free virtual = 24596
# report_utilization -hierarchical -file digilent_arty_a7_utilization_hierarchical_place.rpt
# report_utilization -file digilent_arty_a7_utilization_place.rpt
# report_io -file digilent_arty_a7_io.rpt
report_io: Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.17 . Memory (MB): peak = 2807.223 ; gain = 0.000 ; free physical = 254 ; free virtual = 24587
# report_control_sets -verbose -file digilent_arty_a7_control_sets.rpt
report_control_sets: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2807.223 ; gain = 0.000 ; free physical = 256 ; free virtual = 24588
# report_clock_utilization -file digilent_arty_a7_clock_utilization.rpt
# route_design
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
Phase 1 Build RT Design
Checksum: PlaceDB: 5a95ad7 ConstDB: 0 ShapeSum: 45a6c545 RouteDB: 0
Post Restoration Checksum: NetGraph: 1173b3df | NumContArr: 26c213c8 | Constraints: c2a8fa9d | Timing: c2a8fa9d
Phase 1 Build RT Design | Checksum: 1bd87bce1
Time (s): cpu = 00:01:25 ; elapsed = 00:01:12 . Memory (MB): peak = 2807.223 ; gain = 0.000 ; free physical = 758 ; free virtual = 25122
Phase 2 Router Initialization
Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 1bd87bce1
Time (s): cpu = 00:01:26 ; elapsed = 00:01:12 . Memory (MB): peak = 2807.223 ; gain = 0.000 ; free physical = 758 ; free virtual = 25122
Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 1bd87bce1
Time (s): cpu = 00:01:26 ; elapsed = 00:01:12 . Memory (MB): peak = 2807.223 ; gain = 0.000 ; free physical = 758 ; free virtual = 25122
Number of Nodes with overlaps = 0
Phase 2.3 Update Timing
Phase 2.3 Update Timing | Checksum: 387c952e7
Time (s): cpu = 00:01:39 ; elapsed = 00:01:19 . Memory (MB): peak = 2807.223 ; gain = 0.000 ; free physical = 773 ; free virtual = 25138
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.590 | TNS=-15.295| WHS=-0.605 | THS=-276.189|
Router Utilization Summary
Global Vertical Routing Utilization = 0.00826914 %
Global Horizontal Routing Utilization = 0.00532822 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 5393
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 5357
Number of Partially Routed Nets = 36
Number of Node Overlaps = 26
Phase 2 Router Initialization | Checksum: 314ff1f96
Time (s): cpu = 00:01:45 ; elapsed = 00:01:22 . Memory (MB): peak = 2807.223 ; gain = 0.000 ; free physical = 749 ; free virtual = 25114
Phase 3 Initial Routing
Phase 3.1 Global Routing
Phase 3.1 Global Routing | Checksum: 314ff1f96
Time (s): cpu = 00:01:45 ; elapsed = 00:01:22 . Memory (MB): peak = 2807.223 ; gain = 0.000 ; free physical = 749 ; free virtual = 25114
Phase 3.2 Initial Net Routing
Phase 3.2 Initial Net Routing | Checksum: 269e9475b
Time (s): cpu = 00:01:51 ; elapsed = 00:01:24 . Memory (MB): peak = 2807.223 ; gain = 0.000 ; free physical = 753 ; free virtual = 25118
Phase 3 Initial Routing | Checksum: 269e9475b
Time (s): cpu = 00:01:51 ; elapsed = 00:01:24 . Memory (MB): peak = 2807.223 ; gain = 0.000 ; free physical = 751 ; free virtual = 25116
INFO: [Route 35-580] Design has 4 pins with tight setup and hold constraints.
The top 5 pins with tight setup and hold constraints:
+====================+===================+==============================================+
| Launch Setup Clock | Launch Hold Clock | Pin |
+====================+===================+==============================================+
| sys_clk_pin | sys_clk_pin | Core/Control_Unit/FSM_onehot_state_reg[12]/D |
| sys_clk_pin | sys_clk_pin | Core/Control_Unit/FSM_onehot_state_reg[36]/D |
| sys_clk_pin | sys_clk_pin | Core/Control_Unit/FSM_onehot_state_reg[4]/D |
| sys_clk_pin | sys_clk_pin | Core/Control_Unit/FSM_onehot_state_reg[14]/D |
+--------------------+-------------------+----------------------------------------------+
File with complete list of pins: tight_setup_hold_pins.txt
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
Number of Nodes with overlaps = 2319
Number of Nodes with overlaps = 1030
Number of Nodes with overlaps = 639
Number of Nodes with overlaps = 356
Number of Nodes with overlaps = 174
Number of Nodes with overlaps = 84
Number of Nodes with overlaps = 53
Number of Nodes with overlaps = 36
Number of Nodes with overlaps = 11
Number of Nodes with overlaps = 4
Number of Nodes with overlaps = 2
Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-2.190 | TNS=-373.259| WHS=N/A | THS=N/A |
Phase 4.1 Global Iteration 0 | Checksum: 17174940f
Time (s): cpu = 00:03:21 ; elapsed = 00:02:19 . Memory (MB): peak = 2807.223 ; gain = 0.000 ; free physical = 752 ; free virtual = 25117
Phase 4.2 Global Iteration 1
Number of Nodes with overlaps = 687
Number of Nodes with overlaps = 460
Number of Nodes with overlaps = 275
Number of Nodes with overlaps = 141
Number of Nodes with overlaps = 100
Number of Nodes with overlaps = 53
Number of Nodes with overlaps = 37
Number of Nodes with overlaps = 26
Number of Nodes with overlaps = 28
Number of Nodes with overlaps = 15
Number of Nodes with overlaps = 3
Number of Nodes with overlaps = 6
Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-1.808 | TNS=-194.969| WHS=N/A | THS=N/A |
Phase 4.2 Global Iteration 1 | Checksum: 2f0f077ec
Time (s): cpu = 00:04:01 ; elapsed = 00:02:44 . Memory (MB): peak = 2807.223 ; gain = 0.000 ; free physical = 750 ; free virtual = 25115
Phase 4.3 Global Iteration 2
Number of Nodes with overlaps = 1310
Number of Nodes with overlaps = 629
Number of Nodes with overlaps = 266
Number of Nodes with overlaps = 137
Number of Nodes with overlaps = 89
Number of Nodes with overlaps = 55
Number of Nodes with overlaps = 26
Number of Nodes with overlaps = 10
Number of Nodes with overlaps = 9
Number of Nodes with overlaps = 5
Number of Nodes with overlaps = 1
Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-1.767 | TNS=-142.841| WHS=N/A | THS=N/A |
Phase 4.3 Global Iteration 2 | Checksum: 32f9fec6d
Time (s): cpu = 00:04:52 ; elapsed = 00:03:12 . Memory (MB): peak = 2807.223 ; gain = 0.000 ; free physical = 754 ; free virtual = 25119
Phase 4 Rip-up And Reroute | Checksum: 32f9fec6d
Time (s): cpu = 00:04:52 ; elapsed = 00:03:12 . Memory (MB): peak = 2807.223 ; gain = 0.000 ; free physical = 753 ; free virtual = 25118
Phase 5 Delay and Skew Optimization
Phase 5.1 Delay CleanUp
Phase 5.1.1 Update Timing
Phase 5.1.1 Update Timing | Checksum: 354442571
Time (s): cpu = 00:04:55 ; elapsed = 00:03:13 . Memory (MB): peak = 2807.223 ; gain = 0.000 ; free physical = 754 ; free virtual = 25119
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-1.680 | TNS=-135.521| WHS=N/A | THS=N/A |
Number of Nodes with overlaps = 0
Phase 5.1 Delay CleanUp | Checksum: 26afe95c0
Time (s): cpu = 00:04:57 ; elapsed = 00:03:14 . Memory (MB): peak = 2807.223 ; gain = 0.000 ; free physical = 748 ; free virtual = 25113
Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 26afe95c0
Time (s): cpu = 00:04:57 ; elapsed = 00:03:14 . Memory (MB): peak = 2807.223 ; gain = 0.000 ; free physical = 748 ; free virtual = 25113
Phase 5 Delay and Skew Optimization | Checksum: 26afe95c0
Time (s): cpu = 00:04:57 ; elapsed = 00:03:14 . Memory (MB): peak = 2807.223 ; gain = 0.000 ; free physical = 748 ; free virtual = 25113
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 28360dad1
Time (s): cpu = 00:05:01 ; elapsed = 00:03:16 . Memory (MB): peak = 2807.223 ; gain = 0.000 ; free physical = 740 ; free virtual = 25105
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-1.668 | TNS=-120.708| WHS=0.049 | THS=0.000 |
Phase 6.1 Hold Fix Iter | Checksum: 1d6ad91be
Time (s): cpu = 00:05:01 ; elapsed = 00:03:16 . Memory (MB): peak = 2807.223 ; gain = 0.000 ; free physical = 740 ; free virtual = 25105
Phase 6 Post Hold Fix | Checksum: 1d6ad91be
Time (s): cpu = 00:05:01 ; elapsed = 00:03:16 . Memory (MB): peak = 2807.223 ; gain = 0.000 ; free physical = 740 ; free virtual = 25105
Phase 7 Route finalize
Router Utilization Summary
Global Vertical Routing Utilization = 1.99186 %
Global Horizontal Routing Utilization = 2.57687 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 0
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 0
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
--GLOBAL Congestion:
Utilization threshold used for congestion level computation: 0.85
Congestion Report
North Dir 1x1 Area, Max Cong = 72.0721%, No Congested Regions.
South Dir 1x1 Area, Max Cong = 64.8649%, No Congested Regions.
East Dir 1x1 Area, Max Cong = 82.3529%, No Congested Regions.
West Dir 1x1 Area, Max Cong = 86.7647%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile):
INT_R_X37Y45 -> INT_R_X37Y45
------------------------------
Reporting congestion hotspots
------------------------------
Direction: North
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: South
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: East
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: West
----------------
Congested clusters found at Level 0
Effective congestion level: 1 Aspect Ratio: 0.5 Sparse Ratio: 0.5
Phase 7 Route finalize | Checksum: 1d6ad91be
Time (s): cpu = 00:05:01 ; elapsed = 00:03:16 . Memory (MB): peak = 2807.223 ; gain = 0.000 ; free physical = 740 ; free virtual = 25105
Phase 8 Verifying routed nets
Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 1d6ad91be
Time (s): cpu = 00:05:01 ; elapsed = 00:03:16 . Memory (MB): peak = 2807.223 ; gain = 0.000 ; free physical = 740 ; free virtual = 25105
Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 1dd6d4443
Time (s): cpu = 00:05:03 ; elapsed = 00:03:18 . Memory (MB): peak = 2807.223 ; gain = 0.000 ; free physical = 737 ; free virtual = 25102
Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=-1.668 | TNS=-120.708| WHS=0.049 | THS=0.000 |
WARNING: [Route 35-328] Router estimated timing not met.
Resolution: For a complete and accurate timing signoff, report_timing_summary must be run after route_design. Alternatively, route_design can be run with the -timing_summary option to enable a complete timing signoff at the end of route_design.
Phase 10 Post Router Timing | Checksum: 1dd6d4443
Time (s): cpu = 00:05:06 ; elapsed = 00:03:19 . Memory (MB): peak = 2807.223 ; gain = 0.000 ; free physical = 738 ; free virtual = 25103
INFO: [Route 35-16] Router Completed Successfully
Phase 11 Post-Route Event Processing
Phase 11 Post-Route Event Processing | Checksum: 16bdd32a3
Time (s): cpu = 00:05:07 ; elapsed = 00:03:20 . Memory (MB): peak = 2807.223 ; gain = 0.000 ; free physical = 738 ; free virtual = 25103
Ending Routing Task | Checksum: 16bdd32a3
Time (s): cpu = 00:05:07 ; elapsed = 00:03:20 . Memory (MB): peak = 2807.223 ; gain = 0.000 ; free physical = 745 ; free virtual = 25110
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
15 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:05:11 ; elapsed = 00:03:23 . Memory (MB): peak = 2807.223 ; gain = 0.000 ; free physical = 739 ; free virtual = 25104
# report_timing_summary -no_header -no_detailed_paths
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------
Enable Multi Corner Analysis : Yes
Enable Pessimism Removal : Yes
Pessimism Removal Resolution : Nearest Common Node
Enable Input Delay Default Clock : No
Enable Preset / Clear Arcs : No
Disable Flight Delays : No
Ignore I/O Paths : No
Timing Early Launch at Borrowing Latches : No
Borrow Time for Max Delay Exceptions : Yes
Merge Timing Exceptions : Yes
Inter-SLR Compensation : Conservative
Corner Analyze Analyze
Name Max Paths Min Paths
------ --------- ---------
Slow Yes Yes
Fast Yes Yes
------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------
No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations.
check_timing report
Table of Contents
-----------------
1. checking no_clock (0)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (0)
5. checking no_input_delay (1)
6. checking no_output_delay (1)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)
1. checking no_clock (0)
------------------------
There are 0 register/latch pins with no clock.
2. checking constant_clock (0)
------------------------------
There are 0 register/latch pins with constant_clock.
3. checking pulse_width_clock (0)
---------------------------------
There are 0 register/latch pins which need pulse_width check
4. checking unconstrained_internal_endpoints (0)
------------------------------------------------
There are 0 pins that are not constrained for maximum delay.
There are 0 pins that are not constrained for maximum delay due to constant clock.
5. checking no_input_delay (1)
------------------------------
There is 1 input port with no input delay specified. (HIGH)
There are 0 input ports with no input delay but user has a false path constraint.
6. checking no_output_delay (1)
-------------------------------
There is 1 port with no output delay specified. (HIGH)
There are 0 ports with no output delay but user has a false path constraint
There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
7. checking multiple_clock (0)
------------------------------
There are 0 register/latch pins with multiple clocks.
8. checking generated_clocks (0)
--------------------------------
There are 0 generated clocks that are not connected to a clock source.
9. checking loops (0)
---------------------
There are 0 combinational loops in the design.
10. checking partial_input_delay (0)
------------------------------------
There are 0 input ports with partial input delay specified.
11. checking partial_output_delay (0)
-------------------------------------
There are 0 ports with partial output delay specified.
12. checking latch_loops (0)
----------------------------
There are 0 combinational latch loops in the design through latch input
------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------
WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
-1.668 -120.413 350 16591 0.050 0.000 0 16591 3.750 0.000 0 3607
Timing constraints are not met.
------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------
Clock Waveform(ns) Period(ns) Frequency(MHz)
----- ------------ ---------- --------------
sck {0.000 50.000} 100.000 10.000
sys_clk_pin {0.000 5.000} 10.000 100.000
------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------
Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
sys_clk_pin -1.668 -120.413 350 16591 0.050 0.000 0 16591 3.750 0.000 0 3607
------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------
From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
# report_route_status -file digilent_arty_a7_route_status.rpt
# report_drc -file digilent_arty_a7_drc.rpt
Command: report_drc -file digilent_arty_a7_drc.rpt
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/eda/vivado/Vivado/2023.2/data/ip'.
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /var/jenkins_home/workspace/Risco-5/Risco-5/digilent_arty_a7_drc.rpt.
report_drc completed successfully
# report_timing_summary -datasheet -max_paths 10 -file digilent_arty_a7_timing.rpt
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
# report_power -file digilent_arty_a7_power.rpt
Command: report_power -file digilent_arty_a7_power.rpt
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
0 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
# write_bitstream -force "digilent_arty_a7_100t.bit"
Command: write_bitstream -force digilent_arty_a7_100t.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 8 threads
WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND
set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0
Refer to the device configuration user guide for more information.
WARNING: [DRC DPOP-1] PREG Output pipelining: DSP Core/Mdu/acumulador0 output Core/Mdu/acumulador0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
WARNING: [DRC DPOP-1] PREG Output pipelining: DSP Core/Mdu/acumulador0__0 output Core/Mdu/acumulador0__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
WARNING: [DRC DPOP-2] MREG Output pipelining: DSP Core/Mdu/acumulador0 multiplier stage Core/Mdu/acumulador0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
WARNING: [DRC DPOP-2] MREG Output pipelining: DSP Core/Mdu/acumulador0__0 multiplier stage Core/Mdu/acumulador0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
WARNING: [DRC DPOP-2] MREG Output pipelining: DSP Core/Mdu/acumulador_reg multiplier stage Core/Mdu/acumulador_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
WARNING: [DRC DPOP-2] MREG Output pipelining: DSP Core/Mdu/acumulador_reg__0 multiplier stage Core/Mdu/acumulador_reg__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 7 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Writing bitstream ./digilent_arty_a7_100t.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-83] Releasing license: Implementation
9 Infos, 7 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:34 ; elapsed = 00:00:33 . Memory (MB): peak = 3141.840 ; gain = 250.039 ; free physical = 400 ; free virtual = 24769
# exit
INFO: [Common 17-206] Exiting Vivado at Thu Mar 6 20:22:28 2025...
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash digilent_arty_a7_100t)
[Pipeline] dir
Running in /var/jenkins_home/workspace/Risco-5/Risco-5
[Pipeline] {
[Pipeline] echo
Flashing FPGA digilent_arty_a7_100t.
[Pipeline] sh
+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p Risco-5 -b digilent_arty_a7_100t -l
Final configuration file generated at /var/jenkins_home/workspace/Risco-5/Risco-5/build_digilent_arty_a7_100t.tcl
Makefile executed successfully.
Makefile output:
Flashing the FPGA...
/eda/oss-cad-suite/bin/openFPGALoader -b arty_a7_100t digilent_arty_a7_100t.bit
empty
Jtag frequency : requested 10.00MHz -> real 10.00MHz
Open file DONE
Parse file DONE
load program
Load SRAM: [=============== ] 30.00%
Load SRAM: [=============================== ] 62.00%
Load SRAM: [=============================================== ] 94.00%
Load SRAM: [===================================================] 100.00%
Done
Shift IR 35
ir: 1 isc_done 1 isc_ena 0 init 1 done 1
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Test digilent_arty_a7_100t)
[Pipeline] echo
Testing FPGA digilent_arty_a7_100t.
[Pipeline] dir
Running in /var/jenkins_home/workspace/Risco-5/Risco-5
[Pipeline] {
[Pipeline] sh
+ echo Test for FPGA in /dev/ttyUSB1
Test for FPGA in /dev/ttyUSB1
[Pipeline] echo
python3 /eda/processor_ci_tests/test_runner/run.py --config "/eda/processor_ci_tests/test_runner/config.json" --port /dev/ttyUSB1
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Lock released on resource [Resource: digilent_arty_a7_100t]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Declarative: Post Actions)
[Pipeline] junit
Recording test results
[Checks API] No suitable checks publisher found.
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
Finished: UNSTABLE
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