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Start of Pipeline - (8 min 24 sec in block)
node - (8 min 23 sec in block)
node block - (8 min 23 sec in block)
stage - (2.4 sec in block)Git Clone
stage block (Git Clone) - (1.9 sec in block)
sh - (0.46 sec in self)rm -rf Risco-5
sh - (1.2 sec in self)git clone --recursive --depth=1 https://github.com/JN513/Risco-5.git Risco-5
stage - (1.7 sec in block)Simulation
stage block (Simulation) - (1.2 sec in block)
dir - (0.87 sec in block)Risco-5
dir block - (0.6 sec in block)
sh - (0.41 sec in self)/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -I src/core/ -s soc_tb src/core/alu.v src/core/alu_control.v src/core/control_unit.v src/core/core.v src/core/csr_unit.v src/core/immediate_generator.v src/core/mdu.v src/core/mux.v src/core/pc.v src/core/registers.v tests/soc_test.v src/peripheral/bus.v src/peripheral/fifo.v src/peripheral/gpios.v src/peripheral/gpio.v src/peripheral/leds.v src/peripheral/memory.v src/peripheral/pwm.v src/peripheral/soc.v src/peripheral/uart_rx.v src/peripheral/uart_tx.v src/peripheral/uart.v
stage - (1.7 sec in block)Utilities
stage block (Utilities) - (1.2 sec in block)
dir - (0.88 sec in block)Risco-5
dir block - (0.61 sec in block)
sh - (0.4 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config.json -o /jenkins/processor_ci_utils/labels.json
stage - (8 min 16 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (8 min 15 sec in block)
parallel - (8 min 15 sec in block)
parallel block (Branch: colorlight_i9) - (51 ms in block)
stage - (8 min 14 sec in block)colorlight_i9
stage block (colorlight_i9) - (8 min 13 sec in block)
lock - (8 min 13 sec in block)colorlight_i9
lock block - (8 min 12 sec in block)
stage - (7 min 53 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (7 min 53 sec in block)
dir - (7 min 52 sec in block)Risco-5
dir block - (7 min 52 sec in block)
echo - (0.16 sec in self)Starting synthesis for FPGA colorlight_i9.
sh - (7 min 51 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p Risco-5 -b colorlight_i9
stage - (16 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (16 sec in block)
dir - (15 sec in block)Risco-5
dir block - (15 sec in block)
echo - (0.16 sec in self)Flashing FPGA colorlight_i9.
sh - (15 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p Risco-5 -b colorlight_i9 -l
stage - (1.6 sec in block)Test colorlight_i9
stage block (Test colorlight_i9) - (1.4 sec in block)
echo - (0.2 sec in self)Testing FPGA colorlight_i9.
dir - (0.9 sec in block)Risco-5
dir block - (0.63 sec in block)
sh - (0.42 sec in self)echo "Test for FPGA in /dev/ttyACM0"
parallel block (Branch: digilent_nexys4_ddr) - (46 sec in block)
stage - (45 sec in block)digilent_nexys4_ddr
stage block (digilent_nexys4_ddr) - (45 sec in block)
lock - (44 sec in block)digilent_nexys4_ddr
lock block - (43 sec in block)
stage - (41 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (40 sec in block)
dir - (40 sec in block)Risco-5
dir block - (39 sec in block)
echo - (0.17 sec in self)Starting synthesis for FPGA digilent_nexys4_ddr.
sh - (39 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p Risco-5 -b digilent_nexys4_ddr
stage - (0.99 sec in block)Flash digilent_nexys4_ddr
stage block (Flash digilent_nexys4_ddr) - (0.38 sec in block)
getContext - (0.17 sec in self)
stage - (0.69 sec in block)Test digilent_nexys4_ddr
stage block (Test digilent_nexys4_ddr) - (0.38 sec in block)
getContext - (0.17 sec in self)
stage - (0.75 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.5 sec in block)
junit - (0.25 sec in self)**/test-reports/*.xml