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Console Output

+ cd Risco-5/fpga/nexys4_ddr
+ /eda/oss-cad-suite/bin/openFPGALoader -b nexys_a7_100 ./build/out.bit
empty
Jtag frequency : requested 6.00MHz   -> real 6.00MHz  
Parse file DONE
Erase SRAM Load SRAM 
Load SRAM: [======                                            ] 10.28%
Load SRAM: [===========                                       ] 20.56%
Load SRAM: [================                                  ] 30.83%
Load SRAM: [=====================                             ] 41.11%
Load SRAM: [==========================                        ] 51.39%
Load SRAM: [===============================                   ] 61.67%
Load SRAM: [====================================              ] 71.94%
Load SRAM: [==========================================        ] 82.22%
Load SRAM: [===============================================   ] 92.50%
Load SRAM: [==================================================] 100.00%
Done
DONE