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State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
IDLE | 001 | 00
OPERATE | 010 | 01
FINISH | 100 | 10
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_mul_reg' using encoding 'one-hot' in module 'MDU'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FETCH | 00000000000000000000000000000000000000000000000001 | 000000
VALIDATE_FETCH | 00000000000000000000000000000000000000000000000010 | 101110
DECODE | 00000000000000000000000000000000000000000000000100 | 000001
MEMADR | 00000000000000000000000000000000000000000000001000 | 000010
MEMREAD_UNALIGNED | 00000000000000000000000000000000000000000000010000 | 010110
LOAD_FIRST_BLOCK | 00000000000000000000000000000000000000000000100000 | 010000
SAVE_FIRST_BLOCK | 00000000000000000000000000000000000000000001000000 | 010001
CALC_NEXT_ADDRESS | 00000000000000000000000000000000000000000010000000 | 010010
READ_SECOND_BLOCK | 00000000000000000000000000000000000000000100000000 | 010011
LOAD_SECOND_BLOCK | 00000000000000000000000000000000000000001000000000 | 010100
MERGE_BLOCKS | 00000000000000000000000000000000000000010000000000 | 010101
FILTER_ALU_WB | 00000000000000000000000000000000000000100000000000 | 010111
MEMREAD | 00000000000000000000000000000000000001000000000000 | 000011
MEMWB | 00000000000000000000000000000000000010000000000000 | 000100
MEMWRITE_UNALIGNED | 00000000000000000000000000000000000100000000000000 | 011000
GEN_FIRST_BLOCK_PART_1 | 00000000000000000000000000000000001000000000000000 | 011001
GEN_FIRST_BLOCK_PART_2 | 00000000000000000000000000000000010000000000000000 | 011010
GEN_SECOND_BLOCK_PART_1 | 00000000000000000000000000000000100000000000000000 | 011011
GEN_SECOND_BLOCK_PART_2 | 00000000000000000000000000000001000000000000000000 | 011100
MERGE_WRITE_BLOCKS | 00000000000000000000000000000010000000000000000000 | 011101
SWAP_VALUE_DIRECTION | 00000000000000000000000000000100000000000000000000 | 011110
CLEAR_VALUE_HALF_BYTE_ONE_BLOCK | 00000000000000000000000000001000000000000000000000 | 100010
CLEAR_VALUE_HALF_BYTE_ONE_BLOCK_2 | 00000000000000000000000000010000000000000000000000 | 100011
CLEAR_VALUE_HALF_BYTE_ONE_BLOCK_3 | 00000000000000000000000000100000000000000000000000 | 100100
CLEAR_VALUE | 00000000000000000000000001000000000000000000000000 | 011111
MERGE_WRITE_VALUE_1 | 00000000000000000000000010000000000000000000000000 | 100000
WRITE_VALUE_1 | 00000000000000000000000100000000000000000000000000 | 100001
CALC_SECOND_BLOCK_ADDRESS_TO_WRITE | 00000000000000000000001000000000000000000000000000 | 100101
READ_SECOND_BLOCK_TO_WRITE | 00000000000000000000010000000000000000000000000000 | 100110
LOAD_SECOND_BLOCK_TO_WRITE | 00000000000000000000100000000000000000000000000000 | 100111
LOAD_SECOND_BLOCK_TO_WRITE_2 | 00000000000000000001000000000000000000000000000000 | 101000
SWAP_VALUE_DIRECTION_2 | 00000000000000000010000000000000000000000000000000 | 101001
CLEAR_VALUE_PART_2 | 00000000000000000100000000000000000000000000000000 | 101010
CLEAR_VALUE_PART_2_1 | 00000000000000001000000000000000000000000000000000 | 101011
MERGE_WRITE_VALUE_2 | 00000000000000010000000000000000000000000000000000 | 101100
WRITE_VALUE_2 | 00000000000000100000000000000000000000000000000000 | 101101
MEMWRITE | 00000000000001000000000000000000000000000000000000 | 000101
EXECUTER | 00000000000010000000000000000000000000000000000000 | 000110
EXECUTE_MDU | 00000000000100000000000000000000000000000000000000 | 101111
MDU_WAIT | 00000000001000000000000000000000000000000000000000 | 110000
MDU_WB | 00000000010000000000000000000000000000000000000000 | 110001
EXECUTEI | 00000000100000000000000000000000000000000000000000 | 001000
JAL | 00000001000000000000000000000000000000000000000000 | 001001
BRANCH | 00000010000000000000000000000000000000000000000000 | 001010
AUIPC | 00000100000000000000000000000000000000000000000000 | 001100
LUI | 00001000000000000000000000000000000000000000000000 | 001101
JALR_PC | 00010000000000000000000000000000000000000000000000 | 001110
JALR | 00100000000000000000000000000000000000000000000000 | 001011
ALUWB | 01000000000000000000000000000000000000000000000000 | 000111
EXECUTECSR | 10000000000000000000000000000000000000000000000000 | 001111
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'Control_Unit'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FSM_IDLE | 00 | 000
FSM_START | 11 | 001
FSM_RECV | 10 | 010
FSM_STOP | 01 | 011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tool_rx'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FSM_IDLE | 00 | 000
FSM_START | 11 | 001
FSM_SEND | 10 | 010
FSM_STOP | 01 | 011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tool_tx'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
IDLE | 0000 | 0000
COPY_WRITE_BUFFER | 0001 | 0100
WRITE | 0010 | 0010
READ | 0011 | 0001
READ_RX_FIFO_EMPTY | 0100 | 0110
READ_TX_FIFO_EMPTY | 0101 | 0111
READ_RX_FIFO_FULL | 0110 | 1000
READ_TX_FIFO_FULL | 0111 | 1001
WB | 1000 | 0101
FINISH | 1001 | 0011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'UART'
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 2288.020 ; gain = 664.281 ; free physical = 242 ; free virtual = 22781
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 32 Bit Adders := 7
3 Input 32 Bit Adders := 2
2 Input 10 Bit Adders := 2
2 Input 6 Bit Adders := 6
2 Input 5 Bit Adders := 1
2 Input 4 Bit Adders := 2
2 Input 3 Bit Adders := 2
2 Input 2 Bit Adders := 1
+---XORs :
2 Input 32 Bit XORs := 1
+---XORs :
2 Bit Wide XORs := 1
+---Registers :
64 Bit Registers := 4
32 Bit Registers := 53
16 Bit Registers := 4
10 Bit Registers := 2
8 Bit Registers := 8
6 Bit Registers := 5
4 Bit Registers := 2
3 Bit Registers := 1
2 Bit Registers := 1
1 Bit Registers := 18
+---Multipliers :
32x32 Multipliers := 1
+---RAMs :
16K Bit (512 X 32 bit) RAMs := 1
128 Bit (16 X 8 bit) RAMs := 2
+---Muxes :
4 Input 64 Bit Muxes := 2
50 Input 50 Bit Muxes := 1
2 Input 50 Bit Muxes := 19
11 Input 50 Bit Muxes := 1
2 Input 32 Bit Muxes := 12
4 Input 32 Bit Muxes := 4
8 Input 32 Bit Muxes := 1
15 Input 32 Bit Muxes := 1
3 Input 32 Bit Muxes := 1
6 Input 32 Bit Muxes := 1
10 Input 32 Bit Muxes := 2
2 Input 8 Bit Muxes := 3
3 Input 6 Bit Muxes := 1
2 Input 6 Bit Muxes := 4
2 Input 5 Bit Muxes := 1
50 Input 4 Bit Muxes := 1
9 Input 4 Bit Muxes := 1
10 Input 4 Bit Muxes := 2
23 Input 4 Bit Muxes := 1
2 Input 4 Bit Muxes := 3
6 Input 4 Bit Muxes := 1
3 Input 3 Bit Muxes := 1
2 Input 3 Bit Muxes := 4
5 Input 3 Bit Muxes := 1
4 Input 3 Bit Muxes := 2
50 Input 3 Bit Muxes := 3
10 Input 3 Bit Muxes := 2
3 Input 2 Bit Muxes := 1
2 Input 2 Bit Muxes := 17
4 Input 2 Bit Muxes := 5
50 Input 2 Bit Muxes := 2
3 Input 1 Bit Muxes := 6
2 Input 1 Bit Muxes := 78
4 Input 1 Bit Muxes := 6
50 Input 1 Bit Muxes := 12
6 Input 1 Bit Muxes := 12
10 Input 1 Bit Muxes := 8
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 240 (col length:80)
BRAMs: 270 (col length: RAMB18 80 RAMB36 40)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
[80%] Tech-Mapping Phase 3 completed
[90%] Tech-Mapping Phase 4 completed
WARN (NL0002) : The module "ALU_Control" instantiated to "ALU_Control" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":261)
WARN (NL0002) : The module "Immediate_Generator" instantiated to "Immediate_Generator" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":285)
WARN (NL0002) : The module "MUX" instantiated to "PCSourceMUX" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":197)
[95%] Generate netlist file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg" completed
DSP Report: Generating DSP acumulador0, operation Mode is: A*B.
DSP Report: operator acumulador0 is absorbed into DSP acumulador0.
DSP Report: operator acumulador0 is absorbed into DSP acumulador0.
DSP Report: Generating DSP acumulador_reg, operation Mode is: (PCIN>>17)+A*B.
DSP Report: register acumulador_reg is absorbed into DSP acumulador_reg.
DSP Report: operator acumulador0 is absorbed into DSP acumulador_reg.
DSP Report: operator acumulador0 is absorbed into DSP acumulador_reg.
DSP Report: Generating DSP acumulador0, operation Mode is: A*B.
DSP Report: operator acumulador0 is absorbed into DSP acumulador0.
DSP Report: operator acumulador0 is absorbed into DSP acumulador0.
DSP Report: Generating DSP acumulador_reg, operation Mode is: (PCIN>>17)+A*B.
DSP Report: register acumulador_reg is absorbed into DSP acumulador_reg.
DSP Report: operator acumulador0 is absorbed into DSP acumulador_reg.
DSP Report: operator acumulador0 is absorbed into DSP acumulador_reg.
[100%] Generate report file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project_syn.rpt.html" completed
GowinSynthesis finish
Reading netlist file: "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg"
INFO: [Synth 8-6851] RAM (SOC/Memory/memory_reg) has partial Byte Wide Write Enable pattern, however no output register found in fanout of RAM. Recommended to use supported Byte Wide Write Enable template.
Parsing netlist file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg" completed
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[47]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[46]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[45]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[44]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[43]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[42]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[41]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[40]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[39]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[38]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[37]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[36]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[35]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[34]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[33]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[32]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[31]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[30]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[29]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[28]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[27]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[26]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[25]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[24]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[23]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[22]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[21]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[20]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[19]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[18]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[17]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[47]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[46]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[45]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[44]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[43]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[42]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[41]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[40]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[39]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[38]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[37]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[36]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[35]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[34]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[33]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[32]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[31]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[30]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[29]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[28]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[27]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[26]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[25]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[24]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[23]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[22]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[21]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[20]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[19]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[18]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[17]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (FSM_onehot_state_reg[22]) is unused and will be removed from module Control_Unit.
Processing netlist completed
Reading constraint file: "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/pinout.cst"
Physical Constraint parsed completed
Running placement......
Info: at iteration #5: temp = 0.000000, timing cost = 5352, wirelen = 34250
[10%] Placement Phase 0 completed
Info: at iteration #10: temp = 0.000000, timing cost = 4576, wirelen = 32985
[20%] Placement Phase 1 completed
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:32 ; elapsed = 00:00:32 . Memory (MB): peak = 2288.020 ; gain = 664.281 ; free physical = 179 ; free virtual = 22649
---------------------------------------------------------------------------------
Sort Area is acumulador0_3 : 0 0 : 2701 4912 : Used 1 time 0
Sort Area is acumulador0_3 : 0 1 : 2211 4912 : Used 1 time 0
Sort Area is acumulador0_0 : 0 0 : 2158 4062 : Used 1 time 0
Sort Area is acumulador0_0 : 0 1 : 1904 4062 : Used 1 time 0
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Distributed RAM: Preliminary Mapping Report (see note below)
+------------+-----------------------------+-----------+----------------------+-----------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+------------+-----------------------------+-----------+----------------------+-----------------+
|top | SOC/Memory/memory_reg | Implied | 512 x 32 | RAM256X1S x 64 |
|top | SOC/Uart/RX_FIFO/memory_reg | Implied | 16 x 8 | RAM32M x 2 |
|top | SOC/Uart/TX_FIFO/memory_reg | Implied | 16 x 8 | RAM32M x 2 |
+------------+-----------------------------+-----------+----------------------+-----------------+
Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
DSP: Preliminary Mapping Report (see note below. The ' indicates corresponding REG is set)
+------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG |
+------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|MDU | A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|MDU | (PCIN>>17)+A*B | 15 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
|MDU | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|MDU | (PCIN>>17)+A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
+------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Info: at iteration #15: temp = 0.000000, timing cost = 4946, wirelen = 32453
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:38 ; elapsed = 00:00:39 . Memory (MB): peak = 2288.020 ; gain = 664.281 ; free physical = 221 ; free virtual = 22652
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
Info: at iteration #20: temp = 0.000000, timing cost = 4907, wirelen = 32249
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2288.020 ; gain = 664.281 ; free physical = 206 ; free virtual = 22638
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Distributed RAM: Final Mapping Report
+------------+-----------------------------+-----------+----------------------+-----------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+------------+-----------------------------+-----------+----------------------+-----------------+
|top | SOC/Memory/memory_reg | Implied | 512 x 32 | RAM256X1S x 64 |
|top | SOC/Uart/RX_FIFO/memory_reg | Implied | 16 x 8 | RAM32M x 2 |
|top | SOC/Uart/TX_FIFO/memory_reg | Implied | 16 x 8 | RAM32M x 2 |
+------------+-----------------------------+-----------+----------------------+-----------------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
[30%] Placement Phase 2 completed
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 2288.020 ; gain = 664.281 ; free physical = 173 ; free virtual = 22604
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
Info: at iteration #25: temp = 0.000000, timing cost = 4782, wirelen = 32090
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 2288.020 ; gain = 664.281 ; free physical = 184 ; free virtual = 22599
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 2288.020 ; gain = 664.281 ; free physical = 184 ; free virtual = 22599
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:49 ; elapsed = 00:00:49 . Memory (MB): peak = 2288.020 ; gain = 664.281 ; free physical = 180 ; free virtual = 22595
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:49 ; elapsed = 00:00:49 . Memory (MB): peak = 2288.020 ; gain = 664.281 ; free physical = 177 ; free virtual = 22592
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:49 ; elapsed = 00:00:49 . Memory (MB): peak = 2288.020 ; gain = 664.281 ; free physical = 172 ; free virtual = 22586
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:49 ; elapsed = 00:00:49 . Memory (MB): peak = 2288.020 ; gain = 664.281 ; free physical = 182 ; free virtual = 22595
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
DSP Final Report (the ' indicates corresponding REG is set)
+------------+-------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG |
+------------+-------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|MDU | A'*B' | 17 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
|MDU | (PCIN>>17+A'*B')' | 30 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 1 |
|MDU | A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
|MDU | (PCIN>>17+A'*B')' | 17 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 1 |
+------------+-------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+----------+------+
| |Cell |Count |
+------+----------+------+
|1 |BUFG | 2|
|2 |CARRY4 | 143|
|3 |DSP48E1 | 4|
|5 |LUT1 | 179|
|6 |LUT2 | 265|
|7 |LUT3 | 264|
|8 |LUT4 | 305|
|9 |LUT5 | 344|
|10 |LUT6 | 1581|
|11 |MUXF7 | 458|
|12 |MUXF8 | 1|
|13 |RAM256X1S | 64|
|14 |RAM32M | 2|
|15 |RAM32X1D | 4|
|16 |FDRE | 2257|
|17 |FDSE | 5|
|18 |IBUF | 3|
|19 |IOBUF | 8|
|20 |OBUF | 9|
+------+----------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:49 ; elapsed = 00:00:49 . Memory (MB): peak = 2288.020 ; gain = 664.281 ; free physical = 182 ; free virtual = 22595
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 124 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:46 ; elapsed = 00:00:47 . Memory (MB): peak = 2288.020 ; gain = 512.465 ; free physical = 176 ; free virtual = 22589
Synthesis Optimization Complete : Time (s): cpu = 00:00:49 ; elapsed = 00:00:50 . Memory (MB): peak = 2288.020 ; gain = 664.281 ; free physical = 175 ; free virtual = 22589
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2288.020 ; gain = 0.000 ; free physical = 451 ; free virtual = 22865
INFO: [Netlist 29-17] Analyzing 684 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
Finished Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2360.016 ; gain = 0.000 ; free physical = 451 ; free virtual = 22864
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 78 instances were transformed.
IOBUF => IOBUF (IBUF, OBUFT): 8 instances
RAM256X1S => RAM256X1S (MUXF7(x2), MUXF8, RAMS64E(x4)): 64 instances
RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 2 instances
RAM32X1D => RAM32X1D (RAMD32(x2)): 4 instances
Synth Design complete | Checksum: 3d5ab46f
INFO: [Common 17-83] Releasing license: Synthesis
85 Infos, 188 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:59 ; elapsed = 00:00:56 . Memory (MB): peak = 2360.051 ; gain = 1085.320 ; free physical = 453 ; free virtual = 22866
INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2047.598; main = 1777.901; forked = 422.432
INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3225.629; main = 2360.020; forked = 969.656
# opt_design
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command opt_design
Starting DRC Task
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.87 . Memory (MB): peak = 2424.047 ; gain = 63.996 ; free physical = 441 ; free virtual = 22854
Starting Cache Timing Information Task
Info: at iteration #30: temp = 0.000000, timing cost = 4734, wirelen = 32048
Info: at iteration #30: temp = 0.000000, timing cost = 4714, wirelen = 32053
Info: SA placement time 40.43s
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 17bde2d6b
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2472.867 ; gain = 48.820 ; free physical = 336 ; free virtual = 22749
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 39.84 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 10.25 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 9.72 ns
Info: Slack histogram:
Info: legend: * represents 75 endpoint(s)
Info: + represents [1,75) endpoint(s)
Info: [ 14899, 16117) |+
Info: [ 16117, 17335) |+
Info: [ 17335, 18553) |+
Info: [ 18553, 19771) |+
Info: [ 19771, 20989) |****+
Info: [ 20989, 22207) |*************+
Info: [ 22207, 23425) |******+
Info: [ 23425, 24643) |***********+
Info: [ 24643, 25861) |*********+
Info: [ 25861, 27079) |*************+
Info: [ 27079, 28297) |********+
Info: [ 28297, 29515) |********+
Info: [ 29515, 30733) |************************************************************
Info: [ 30733, 31951) |*******************************************+
Info: [ 31951, 33169) |****+
Info: [ 33169, 34387) |*****+
Info: [ 34387, 35605) |**********+
Info: [ 35605, 36823) |********+
Info: [ 36823, 38041) |******+
Info: [ 38041, 39259) |***+
Info: Checksum: 0x98aa7179
Info: Routing globals...
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 47333 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 285 714 | 285 714 | 46725| 0.94 0.94|
Info: 2000 | 483 1516 | 198 802 | 45996| 0.33 1.26|
Info: 3000 | 632 2367 | 149 851 | 45247| 0.33 1.60|
Starting Logic Optimization Task
Phase 1 Initialization
Phase 1.1 Core Generation And Design Setup
Phase 1.1 Core Generation And Design Setup | Checksum: 17bde2d6b
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2721.805 ; gain = 0.000 ; free physical = 163 ; free virtual = 22552
Phase 1.2 Setup Constraints And Sort Netlist
Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 17bde2d6b
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2721.805 ; gain = 0.000 ; free physical = 163 ; free virtual = 22552
Phase 1 Initialization | Checksum: 17bde2d6b
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2721.805 ; gain = 0.000 ; free physical = 163 ; free virtual = 22552
Phase 2 Timer Update And Timing Data Collection
Phase 2.1 Timer Update
Phase 2.1 Timer Update | Checksum: 17bde2d6b
Time (s): cpu = 00:00:00.24 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2721.805 ; gain = 0.000 ; free physical = 164 ; free virtual = 22553
Phase 2.2 Timing Data Collection
Phase 2.2 Timing Data Collection | Checksum: 17bde2d6b
Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.1 . Memory (MB): peak = 2721.805 ; gain = 0.000 ; free physical = 164 ; free virtual = 22553
Phase 2 Timer Update And Timing Data Collection | Checksum: 17bde2d6b
Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.1 . Memory (MB): peak = 2721.805 ; gain = 0.000 ; free physical = 164 ; free virtual = 22553
Phase 3 Retarget
INFO: [Opt 31-1566] Pulled 5 inverters resulting in an inversion of 15 pins
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 3 Retarget | Checksum: 1aaed4520
Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:00.2 . Memory (MB): peak = 2721.805 ; gain = 0.000 ; free physical = 164 ; free virtual = 22553
Retarget | Checksum: 1aaed4520
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 5 cells
Phase 4 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 4 Constant propagation | Checksum: 1c7a38d8c
Time (s): cpu = 00:00:00.44 ; elapsed = 00:00:00.26 . Memory (MB): peak = 2721.805 ; gain = 0.000 ; free physical = 164 ; free virtual = 22553
Constant propagation | Checksum: 1c7a38d8c
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 5 Sweep
Info: 4000 | 803 3196 | 171 829 | 44470| 0.35 1.94|
Phase 5 Sweep | Checksum: 1fdab3f16
Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.33 . Memory (MB): peak = 2721.805 ; gain = 0.000 ; free physical = 164 ; free virtual = 22553
Sweep | Checksum: 1fdab3f16
INFO: [Opt 31-389] Phase Sweep created 8 cells and removed 0 cells
Phase 6 BUFG optimization
Phase 6 BUFG optimization | Checksum: 1fdab3f16
Time (s): cpu = 00:00:00.64 ; elapsed = 00:00:00.39 . Memory (MB): peak = 2753.820 ; gain = 32.016 ; free physical = 164 ; free virtual = 22552
BUFG optimization | Checksum: 1fdab3f16
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
Phase 7 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 7 Shift Register Optimization | Checksum: 1fdab3f16
Time (s): cpu = 00:00:00.64 ; elapsed = 00:00:00.39 . Memory (MB): peak = 2753.820 ; gain = 32.016 ; free physical = 163 ; free virtual = 22552
Shift Register Optimization | Checksum: 1fdab3f16
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 8 Post Processing Netlist
Phase 8 Post Processing Netlist | Checksum: 1840418f9
Time (s): cpu = 00:00:00.66 ; elapsed = 00:00:00.41 . Memory (MB): peak = 2753.820 ; gain = 32.016 ; free physical = 163 ; free virtual = 22552
Post Processing Netlist | Checksum: 1840418f9
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Phase 9 Finalization
Phase 9.1 Finalizing Design Cores and Updating Shapes
Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 9256cb34
Time (s): cpu = 00:00:00.77 ; elapsed = 00:00:00.5 . Memory (MB): peak = 2753.820 ; gain = 32.016 ; free physical = 162 ; free virtual = 22550
Phase 9.2 Verifying Netlist Connectivity
Starting Connectivity Check Task
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2753.820 ; gain = 0.000 ; free physical = 162 ; free virtual = 22550
Phase 9.2 Verifying Netlist Connectivity | Checksum: 9256cb34
Time (s): cpu = 00:00:00.78 ; elapsed = 00:00:00.51 . Memory (MB): peak = 2753.820 ; gain = 32.016 ; free physical = 162 ; free virtual = 22550
Phase 9 Finalization | Checksum: 9256cb34
Time (s): cpu = 00:00:00.78 ; elapsed = 00:00:00.51 . Memory (MB): peak = 2753.820 ; gain = 32.016 ; free physical = 162 ; free virtual = 22550
Opt_design Change Summary
=========================
-------------------------------------------------------------------------------------------------------------------------
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
-------------------------------------------------------------------------------------------------------------------------
| Retarget | 0 | 5 | 0 |
| Constant propagation | 0 | 0 | 0 |
| Sweep | 8 | 0 | 0 |
| BUFG optimization | 0 | 0 | 0 |
| Shift Register Optimization | 0 | 0 | 0 |
| Post Processing Netlist | 0 | 0 | 0 |
-------------------------------------------------------------------------------------------------------------------------
Ending Logic Optimization Task | Checksum: 9256cb34
Time (s): cpu = 00:00:00.79 ; elapsed = 00:00:00.52 . Memory (MB): peak = 2753.820 ; gain = 32.016 ; free physical = 162 ; free virtual = 22550
INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2753.820 ; gain = 0.000 ; free physical = 162 ; free virtual = 22550
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 9256cb34
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2753.820 ; gain = 0.000 ; free physical = 161 ; free virtual = 22550
Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 9256cb34
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2753.820 ; gain = 0.000 ; free physical = 161 ; free virtual = 22550
Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2753.820 ; gain = 0.000 ; free physical = 160 ; free virtual = 22549
Ending Netlist Obfuscation Task | Checksum: 9256cb34
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2753.820 ; gain = 0.000 ; free physical = 160 ; free virtual = 22549
INFO: [Common 17-83] Releasing license: Implementation
19 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2753.820 ; gain = 393.770 ; free physical = 160 ; free virtual = 22549
# place_design
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-83] Releasing license: Implementation
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 8 threads
Info: 5000 | 934 4065 | 131 869 | 43644| 0.39 2.33|
Info: 6000 | 1087 4912 | 153 847 | 42986| 0.45 2.78|
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs
Starting Placer Task
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2785.836 ; gain = 0.000 ; free physical = 162 ; free virtual = 22541
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 724be6b6
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2785.836 ; gain = 0.000 ; free physical = 161 ; free virtual = 22540
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2785.836 ; gain = 0.000 ; free physical = 161 ; free virtual = 22540
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
Info: 7000 | 1228 5771 | 141 859 | 42264| 0.39 3.17|
INFO: [Timing 38-35] Done setting XDC timing constraints.
Info: 8000 | 1361 6638 | 133 867 | 41551| 0.37 3.54|
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 114906623
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.81 . Memory (MB): peak = 2785.836 ; gain = 0.000 ; free physical = 167 ; free virtual = 22546
Phase 1.3 Build Placer Netlist Model
Info: 9000 | 1551 7448 | 190 810 | 40947| 0.31 3.84|
Info: 10000 | 1675 8324 | 124 876 | 40287| 0.32 4.16|
Info: 11000 | 1853 9146 | 178 822 | 39605| 0.41 4.58|
Info: 12000 | 2071 9928 | 218 782 | 39007| 0.37 4.95|
Phase 1.3 Build Placer Netlist Model | Checksum: 1c43bbaca
Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2792.863 ; gain = 7.027 ; free physical = 166 ; free virtual = 22545
Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 1c43bbaca
Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2792.863 ; gain = 7.027 ; free physical = 166 ; free virtual = 22544
Phase 1 Placer Initialization | Checksum: 1c43bbaca
Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2792.863 ; gain = 7.027 ; free physical = 166 ; free virtual = 22544
Phase 2 Global Placement
Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 1c0bb9f3f
Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2792.863 ; gain = 7.027 ; free physical = 161 ; free virtual = 22540
Phase 2.2 Update Timing before SLR Path Opt
Phase 2.2 Update Timing before SLR Path Opt | Checksum: 137da827e
Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2792.863 ; gain = 7.027 ; free physical = 161 ; free virtual = 22540
Phase 2.3 Post-Processing in Floorplanning
Phase 2.3 Post-Processing in Floorplanning | Checksum: 137da827e
Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2792.863 ; gain = 7.027 ; free physical = 161 ; free virtual = 22540
Phase 2.4 Global Placement Core
Info: 13000 | 2242 10757 | 171 829 | 38308| 0.38 5.33|
Info: 14000 | 2469 11530 | 227 773 | 37632| 0.45 5.78|
Info: 15000 | 2657 12342 | 188 812 | 37147| 0.40 6.18|
Info: 16000 | 2866 13133 | 209 791 | 36424| 0.39 6.57|
Info: 17000 | 3027 13972 | 161 839 | 35974| 0.44 7.01|
Info: 18000 | 3196 14803 | 169 831 | 35650| 0.46 7.47|
Info: 19000 | 3419 15580 | 223 777 | 35036| 0.43 7.90|
Info: 20000 | 3656 16343 | 237 763 | 34409| 0.41 8.31|
Info: 21000 | 3841 17158 | 185 815 | 33833| 0.46 8.77|
Info: 22000 | 4085 17914 | 244 756 | 33219| 0.34 9.11|
[50%] Placement Phase 3 completed
Running routing......
Phase 2.4.1 UpdateTiming Before Physical Synthesis
Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 1f31721da
Time (s): cpu = 00:00:19 ; elapsed = 00:00:06 . Memory (MB): peak = 2792.863 ; gain = 7.027 ; free physical = 156 ; free virtual = 22518
Phase 2.4.2 Physical Synthesis In Placer
INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 112 LUT instances to create LUTNM shape
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
INFO: [Physopt 32-1138] End 1 Pass. Optimized 51 nets or LUTs. Breaked 0 LUT, combined 51 existing LUTs and moved 0 existing LUT
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed.
Info: 23000 | 4288 18711 | 203 797 | 32584| 0.33 9.44|
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2792.863 ; gain = 0.000 ; free physical = 162 ; free virtual = 22525
Summary of Physical Synthesis Optimizations
============================================
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| LUT Combining | 0 | 51 | 51 | 0 | 1 | 00:00:00 |
| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Total | 0 | 51 | 51 | 0 | 4 | 00:00:00 |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
Phase 2.4.2 Physical Synthesis In Placer | Checksum: 1126ed5da
Time (s): cpu = 00:00:20 ; elapsed = 00:00:07 . Memory (MB): peak = 2792.863 ; gain = 7.027 ; free physical = 162 ; free virtual = 22525
Info: 24000 | 4502 19497 | 214 786 | 32006| 0.39 9.83|
Info: 25000 | 4713 20286 | 211 789 | 31324| 0.43 10.26|
Phase 2.4 Global Placement Core | Checksum: 1a335469c
Time (s): cpu = 00:00:24 ; elapsed = 00:00:07 . Memory (MB): peak = 2792.863 ; gain = 7.027 ; free physical = 162 ; free virtual = 22525
Phase 2 Global Placement | Checksum: 1a335469c
Time (s): cpu = 00:00:24 ; elapsed = 00:00:07 . Memory (MB): peak = 2792.863 ; gain = 7.027 ; free physical = 162 ; free virtual = 22525
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 11cc7c42d
Time (s): cpu = 00:00:24 ; elapsed = 00:00:07 . Memory (MB): peak = 2792.863 ; gain = 7.027 ; free physical = 162 ; free virtual = 22525
Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 117539596
Time (s): cpu = 00:00:25 ; elapsed = 00:00:07 . Memory (MB): peak = 2792.863 ; gain = 7.027 ; free physical = 162 ; free virtual = 22525
Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 16fed60bf
Time (s): cpu = 00:00:25 ; elapsed = 00:00:08 . Memory (MB): peak = 2792.863 ; gain = 7.027 ; free physical = 162 ; free virtual = 22525
Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 9c34f29e
Time (s): cpu = 00:00:25 ; elapsed = 00:00:08 . Memory (MB): peak = 2792.863 ; gain = 7.027 ; free physical = 162 ; free virtual = 22525
Phase 3.5 Small Shape Detail Placement
Info: 26000 | 4911 21088 | 198 802 | 30586| 0.37 10.63|
Info: 27000 | 5150 21849 | 239 761 | 29923| 0.37 11.00|
Info: 28000 | 5340 22659 | 190 810 | 29284| 0.36 11.36|
Info: 29000 | 5587 23412 | 247 753 | 28742| 0.37 11.73|
Phase 3.5 Small Shape Detail Placement | Checksum: 16ee86e36
Time (s): cpu = 00:00:26 ; elapsed = 00:00:09 . Memory (MB): peak = 2792.863 ; gain = 7.027 ; free physical = 201 ; free virtual = 22535
Phase 3.6 Re-assign LUT pins
Info: 30000 | 5828 24171 | 241 759 | 28061| 0.34 12.07|
[60%] Routing Phase 0 completed
Phase 3.6 Re-assign LUT pins | Checksum: 12ded961f
Time (s): cpu = 00:00:27 ; elapsed = 00:00:09 . Memory (MB): peak = 2792.863 ; gain = 7.027 ; free physical = 151 ; free virtual = 22486
Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: 11635bfbe
Time (s): cpu = 00:00:27 ; elapsed = 00:00:09 . Memory (MB): peak = 2792.863 ; gain = 7.027 ; free physical = 151 ; free virtual = 22486
Phase 3 Detail Placement | Checksum: 11635bfbe
Time (s): cpu = 00:00:27 ; elapsed = 00:00:09 . Memory (MB): peak = 2792.863 ; gain = 7.027 ; free physical = 151 ; free virtual = 22486
Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.
Info: 31000 | 6003 24996 | 175 825 | 27438| 0.35 12.42|
Info: 32000 | 6225 25774 | 222 778 | 26763| 0.42 12.84|
Info: 33000 | 6495 26504 | 270 730 | 26127| 0.46 13.29|
Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 16c82edf1
Phase 4.1.1.1 BUFG Insertion
Starting Physical Synthesis Task
Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
Info: 34000 | 6778 27221 | 283 717 | 25559| 0.40 13.69|
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=9.081 | TNS=0.000 |
Phase 1 Physical Synthesis Initialization | Checksum: 184fb7ad0
Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2792.863 ; gain = 0.000 ; free physical = 151 ; free virtual = 22485
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
Ending Physical Synthesis Task | Checksum: 184fb7ad0
Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.17 . Memory (MB): peak = 2792.863 ; gain = 0.000 ; free physical = 151 ; free virtual = 22485
Phase 4.1.1.1 BUFG Insertion | Checksum: 16c82edf1
Time (s): cpu = 00:00:31 ; elapsed = 00:00:11 . Memory (MB): peak = 2792.863 ; gain = 7.027 ; free physical = 151 ; free virtual = 22485
Phase 4.1.1.2 Post Placement Timing Optimization
INFO: [Place 30-746] Post Placement Timing Summary WNS=9.081. For the most accurate timing information please run report_timing.
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 16658260a
Time (s): cpu = 00:00:31 ; elapsed = 00:00:11 . Memory (MB): peak = 2792.863 ; gain = 7.027 ; free physical = 151 ; free virtual = 22485
Time (s): cpu = 00:00:31 ; elapsed = 00:00:11 . Memory (MB): peak = 2792.863 ; gain = 7.027 ; free physical = 151 ; free virtual = 22485
Phase 4.1 Post Commit Optimization | Checksum: 16658260a
Time (s): cpu = 00:00:31 ; elapsed = 00:00:11 . Memory (MB): peak = 2792.863 ; gain = 7.027 ; free physical = 151 ; free virtual = 22485
Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 16658260a
Time (s): cpu = 00:00:31 ; elapsed = 00:00:11 . Memory (MB): peak = 2792.863 ; gain = 7.027 ; free physical = 238 ; free virtual = 22480
Phase 4.3 Placer Reporting
Phase 4.3.1 Print Estimated Congestion
INFO: [Place 30-612] Post-Placement Estimated Congestion
____________________________________________________
| | Global Congestion | Short Congestion |
| Direction | Region Size | Region Size |
|___________|___________________|___________________|
| North| 1x1| 1x1|
|___________|___________________|___________________|
| South| 1x1| 2x2|
|___________|___________________|___________________|
| East| 1x1| 1x1|
|___________|___________________|___________________|
| West| 1x1| 1x1|
|___________|___________________|___________________|
Phase 4.3.1 Print Estimated Congestion | Checksum: 16658260a
Time (s): cpu = 00:00:31 ; elapsed = 00:00:11 . Memory (MB): peak = 2792.863 ; gain = 7.027 ; free physical = 275 ; free virtual = 22477
Phase 4.3 Placer Reporting | Checksum: 16658260a
Time (s): cpu = 00:00:31 ; elapsed = 00:00:11 . Memory (MB): peak = 2792.863 ; gain = 7.027 ; free physical = 275 ; free virtual = 22477
Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2792.863 ; gain = 0.000 ; free physical = 275 ; free virtual = 22477
Time (s): cpu = 00:00:31 ; elapsed = 00:00:11 . Memory (MB): peak = 2792.863 ; gain = 7.027 ; free physical = 275 ; free virtual = 22477
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 9baa4429
Time (s): cpu = 00:00:31 ; elapsed = 00:00:11 . Memory (MB): peak = 2792.863 ; gain = 7.027 ; free physical = 273 ; free virtual = 22475
Ending Placer Task | Checksum: 9a42b471
Time (s): cpu = 00:00:31 ; elapsed = 00:00:11 . Memory (MB): peak = 2792.863 ; gain = 7.027 ; free physical = 276 ; free virtual = 22478
29 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:12 . Memory (MB): peak = 2792.863 ; gain = 39.043 ; free physical = 276 ; free virtual = 22478
# report_utilization -hierarchical -file digilent_nexys4ddr_utilization_hierarchical_place.rpt
# report_utilization -file digilent_nexys4ddr_utilization_place.rpt
Info: 35000 | 7073 27926 | 295 705 | 25004| 0.44 14.13|
# report_io -file digilent_nexys4ddr_io.rpt
Info: 36000 | 7339 28660 | 266 734 | 24429| 0.39 14.52|
report_io: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.18 . Memory (MB): peak = 2792.863 ; gain = 0.000 ; free physical = 263 ; free virtual = 22464
# report_control_sets -verbose -file digilent_nexys4ddr_control_sets.rpt
report_control_sets: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.12 . Memory (MB): peak = 2792.863 ; gain = 0.000 ; free physical = 262 ; free virtual = 22463
# report_clock_utilization -file digilent_nexys4ddr_clock_utilization.rpt
Info: 37000 | 7675 29324 | 336 664 | 23914| 0.43 14.95|
Info: 38000 | 7975 30024 | 300 700 | 23688| 0.37 15.32|
# route_design
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 8 threads
Info: 39000 | 8248 30751 | 273 727 | 23195| 0.56 15.88|
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
Phase 1 Build RT Design
Checksum: PlaceDB: 97e8a20e ConstDB: 0 ShapeSum: 25a1263 RouteDB: 0
Info: 40000 | 8533 31466 | 285 715 | 22658| 0.47 16.35|
Info: 41000 | 8874 32125 | 341 659 | 22189| 0.48 16.83|
Info: 42000 | 9192 32807 | 318 682 | 21873| 0.37 17.20|
Info: 43000 | 9477 33522 | 285 715 | 21589| 0.36 17.56|
Info: 44000 | 9832 34167 | 355 645 | 21062| 0.36 17.92|
Info: 45000 | 10220 34779 | 388 612 | 20594| 0.39 18.31|
Info: 46000 | 10636 35363 | 416 584 | 20187| 0.37 18.69|
Info: 47000 | 11043 35956 | 407 593 | 19936| 0.41 19.09|
Info: 48000 | 11408 36591 | 365 635 | 19631| 0.42 19.51|
Info: 49000 | 11775 37224 | 367 633 | 19234| 0.41 19.92|
Info: 50000 | 12183 37816 | 408 592 | 18848| 0.39 20.31|
Info: 51000 | 12591 38408 | 408 592 | 18446| 0.39 20.70|
Info: 52000 | 13027 38947 | 436 539 | 17977| 0.38 21.08|
Info: 53000 | 13449 39507 | 422 560 | 17504| 0.41 21.48|
Info: 54000 | 13830 40089 | 381 582 | 17689| 0.41 21.89|
[70%] Routing Phase 1 completed
Info: 55000 | 13992 40915 | 162 826 | 16971| 0.50 22.40|
Info: 56000 | 14271 41612 | 279 697 | 16783| 0.51 22.91|
Info: 57000 | 14597 42173 | 326 561 | 16162| 0.42 23.33|
Info: 58000 | 14854 42764 | 257 591 | 15463| 0.28 23.61|
Info: 59000 | 15068 43364 | 214 600 | 14720| 0.24 23.85|
Info: 60000 | 15342 43978 | 274 614 | 14066| 0.28 24.13|
Info: 61000 | 15576 44664 | 234 686 | 13332| 0.24 24.37|
Info: 62000 | 15777 45390 | 201 726 | 12630| 0.24 24.61|
Info: 63000 | 16006 46109 | 229 719 | 11889| 0.22 24.83|
Info: 64000 | 16295 46763 | 289 654 | 11196| 0.32 25.16|
Info: 65000 | 16709 47284 | 414 521 | 10656| 0.43 25.58|
Info: 66000 | 17035 47925 | 326 641 | 10006| 0.33 25.91|
Info: 67000 | 17257 48642 | 222 717 | 9343| 0.38 26.29|
Info: 68000 | 17313 49583 | 56 941 | 8405| 0.32 26.61|
Info: 69000 | 17326 50570 | 13 987 | 7420| 0.12 26.73|
Info: 70000 | 17336 51560 | 10 990 | 6431| 0.12 26.85|
Info: 71000 | 17349 52530 | 13 970 | 5444| 0.12 26.97|
Info: 72000 | 17376 53468 | 27 938 | 4471| 0.14 27.11|
Info: 73000 | 17450 54309 | 74 841 | 3558| 0.27 27.38|
Info: 74000 | 17549 55140 | 99 831 | 2665| 0.25 27.63|
Info: 75000 | 17616 55986 | 67 846 | 1751| 0.26 27.88|
Info: 76000 | 17688 56886 | 72 900 | 863| 0.29 28.18|
Info: 76873 | 17699 57311 | 11 425 | 0| 0.20 28.37|
Info: Routing complete.
Info: Router1 time 28.37s
Info: Checksum: 0xc2223912
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: curr total
Info: 0.5 0.5 Source SOC.Core.Control_Unit.state_TRELLIS_FF_Q.Q
Info: 2.1 2.7 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_3_A_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_LUT4_C_Z_LUT4_Z_B_L6MUX21_Z_SD[0] (31,17) -> (18,8)
Info: Sink SOC.Core.RegisterBank.registers.0.2_DO_LUT4_Z.C
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 2.9 Source SOC.Core.RegisterBank.registers.0.2_DO_LUT4_Z.F
Info: 2.0 4.9 Net SOC.Core.Control_Unit.nextstate_LUT4_Z_5_A_LUT4_Z_D_LUT4_Z_C_LUT4_Z_1_C[0] (18,8) -> (32,19)
Info: Sink SOC.Core.RegisterBank.registers.0.2_DO_3_LUT4_B_Z_LUT4_Z.C
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 5.1 Source SOC.Core.RegisterBank.registers.0.2_DO_3_LUT4_B_Z_LUT4_Z.F
Info: 1.3 6.4 Net SOC.Core.Control_Unit.nextstate_LUT4_Z_5_B_LUT4_D_Z_LUT4_Z_B_LUT4_Z_1_C_LUT4_Z_A[3] (32,19) -> (21,18)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_3_A_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_LUT4_C_Z_L6MUX21_Z_SD_LUT4_Z_1.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 6.7 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_3_A_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_LUT4_C_Z_L6MUX21_Z_SD_LUT4_Z_1.F
Info: 0.4 7.1 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_3_A_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_LUT4_C_Z_L6MUX21_Z_SD[5] (21,18) -> (21,18)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_3_A_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_LUT4_C_Z_L6MUX21_Z_SD_LUT4_C.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 7.3 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_3_A_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_LUT4_C_Z_L6MUX21_Z_SD_LUT4_C.OFX
Info: 1.4 8.8 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_3_A_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_LUT4_C_Z[1] (21,18) -> (25,14)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_3_A_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.B
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.4 9.2 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_3_A_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 9.2 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_3_A_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (25,14) -> (25,14)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_3_A_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 9.2 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_3_A_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 9.2 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_3_A_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (25,14) -> (25,14)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_3_A_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/src/core/alu.v:33.26-33.45
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 9.3 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_3_A_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 9.3 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_3_A_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (25,14) -> (25,14)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_3_A_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.4 9.7 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_3_A_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.F
Info: 0.6 10.3 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_3_A_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1[3] (25,14) -> (23,14)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_3_A_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_LUT4_C.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 10.6 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_3_A_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_LUT4_C.F
Info: 0.7 11.3 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_3_A_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_LUT4_C_Z[5] (23,14) -> (23,13)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_3_A_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_LUT4_C_Z_L6MUX21_SD_D1_PFUMX_Z_ALUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 11.5 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_3_A_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_LUT4_C_Z_L6MUX21_SD_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 1.3 12.8 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_3_A_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_LUT4_C_Z_L6MUX21_SD_Z[5] (23,13) -> (23,2)
Info: Sink SOC.Core.Alu.ALU_out_S_L6MUX21_Z_4_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 13.1 Source SOC.Core.Alu.ALU_out_S_L6MUX21_Z_4_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 0.0 13.1 Net SOC.Core.Alu.ALU_out_S_L6MUX21_Z_4_D1 (23,2) -> (23,2)
Info: Sink SOC.Core.Alu.ALU_out_S_L6MUX21_Z_4_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.70-157.72
Info: 0.2 13.3 Source SOC.Core.Alu.ALU_out_S_L6MUX21_Z_4_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 1.1 14.4 Net SOC.Core.alu_out[11] (23,2) -> (23,12)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_4_A_LUT4_C_Z_L6MUX21_SD_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.C
Info: Defined in:
Info: Risco-5/src/core/core.v:60.31-60.38
Info: 0.2 14.6 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_4_A_LUT4_C_Z_L6MUX21_SD_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.F
Info: 0.0 14.6 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_4_A_LUT4_C_Z_L6MUX21_SD_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT (23,12) -> (23,12)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_4_A_LUT4_C_Z_L6MUX21_SD_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.F1
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.46-157.48
Info: 0.2 14.8 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_4_A_LUT4_C_Z_L6MUX21_SD_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 0.0 14.8 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_4_A_LUT4_C_Z_L6MUX21_SD_Z_L6MUX21_Z_D1_L6MUX21_Z_D1 (23,12) -> (23,12)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_4_A_LUT4_C_Z_L6MUX21_SD_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.62-157.64
Info: 0.2 15.0 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_4_A_LUT4_C_Z_L6MUX21_SD_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 0.0 15.0 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_4_A_LUT4_C_Z_L6MUX21_SD_Z_L6MUX21_Z_D1 (23,12) -> (23,12)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_4_A_LUT4_C_Z_L6MUX21_SD_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.70-157.72
Info: 0.2 15.3 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_4_A_LUT4_C_Z_L6MUX21_SD_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 1.2 16.5 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_4_A_LUT4_C_Z_L6MUX21_SD_Z[4] (23,12) -> (30,14)
Info: Sink SOC.Core.Pc.load_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 16.7 Source SOC.Core.Pc.load_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 1.9 18.6 Net SOC.Core.pc_load (30,14) -> (19,4)
Info: Sink SOC.Core.Pc.Output_TRELLIS_FF_Q_18.CE
Info: Defined in:
Info: Risco-5/src/core/core.v:51.32-51.39
Info: 0.0 18.6 Setup SOC.Core.Pc.Output_TRELLIS_FF_Q_18.CE
Info: 4.5 ns logic, 14.1 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: curr total
Info: 0.0 0.0 Source gpios[5]$tr_io.O
Info: 2.9 2.9 Net gpios[5]$TRELLIS_IO_IN (9,71) -> (9,42)
Info: Sink SOC.GPIOS.Gpios[5].data_in_LUT4_B.A
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:7.16-7.21
Info: 0.2 3.1 Source SOC.GPIOS.Gpios[5].data_in_LUT4_B.F
Info: 1.0 4.1 Net SOC.GPIOS.Gpios[5].data_in_LUT4_B_Z[4] (9,42) -> (9,37)
Info: Sink SOC.GPIOS.Gpios[5].data_in_LUT4_B_Z_PFUMX_C0_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 4.4 Source SOC.GPIOS.Gpios[5].data_in_LUT4_B_Z_PFUMX_C0_BLUT_LUT4_Z.OFX
Info: 1.1 5.4 Net SOC.GPIOS.Gpios[5].data_in_LUT4_B_Z_PFUMX_C0_Z[1] (9,37) -> (12,32)
Info: Sink SOC.Core.read_data_LUT4_Z_4.B
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 5.7 Source SOC.Core.read_data_LUT4_Z_4.F
Info: 1.7 7.4 Net SOC.read_data[5] (12,32) -> (19,21)
Info: Sink SOC.Core.instruction_register_TRELLIS_FF_Q_25.M
Info: Defined in:
Info: Risco-5/src/peripheral/soc.v:24.34-24.43
Info: 0.0 7.4 Setup SOC.Core.instruction_register_TRELLIS_FF_Q_25.M
Info: 0.7 ns logic, 6.7 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: curr total
Info: 0.5 0.5 Source SOC.Leds.data_TRELLIS_FF_Q_29.Q
Info: 3.8 4.3 Net SOC.Leds.data[2] (23,27) -> (71,43)
Info: Sink led_LUT4_Z_6.D
Info: Defined in:
Info: Risco-5/src/peripheral/leds.v:19.12-19.16
Info: 0.2 4.5 Source led_LUT4_Z_6.F
Info: 1.7 6.2 Net led[2]$TRELLIS_IO_OUT (71,43) -> (90,44)
Info: Sink led[2]$tr_io.I
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:6.22-6.25
Info: 0.8 ns logic, 5.4 ns routing
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 53.64 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 7.38 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 6.19 ns
Info: Slack histogram:
Info: legend: * represents 84 endpoint(s)
Info: + represents [1,84) endpoint(s)
Info: [ 21358, 22243) |+
Info: [ 22243, 23128) |*+
Info: [ 23128, 24013) |*******+
Info: [ 24013, 24898) |**********+
Info: [ 24898, 25783) |**+
Info: [ 25783, 26668) |*+
Info: [ 26668, 27553) |***+
Info: [ 27553, 28438) |************+
Info: [ 28438, 29323) |*******************+
Info: [ 29323, 30208) |**+
Info: [ 30208, 31093) |+
Info: [ 31093, 31978) |*********+
Info: [ 31978, 32863) |************************************************************
Info: [ 32863, 33748) |********************************+
Info: [ 33748, 34633) |***+
Info: [ 34633, 35518) |**+
Info: [ 35518, 36403) |*******+
Info: [ 36403, 37288) |**********+
Info: [ 37288, 38173) |****+
Info: [ 38173, 39058) |***+
Info: Program finished normally.
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (ECPPACK)
[Pipeline] sh
+ /eda/oss-cad-suite/bin/ecppack --compress --input ./build/out.config --bit ./build/out.bit
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[80%] Routing Phase 2 completed
Post Restoration Checksum: NetGraph: 8beccb3b | NumContArr: 7f5eef54 | Constraints: c2a8fa9d | Timing: c2a8fa9d
Phase 1 Build RT Design | Checksum: 2909dafc9
Time (s): cpu = 00:00:35 ; elapsed = 00:00:28 . Memory (MB): peak = 2792.863 ; gain = 0.000 ; free physical = 605 ; free virtual = 22837
Phase 2 Router Initialization
Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 2909dafc9
Time (s): cpu = 00:00:35 ; elapsed = 00:00:28 . Memory (MB): peak = 2792.863 ; gain = 0.000 ; free physical = 605 ; free virtual = 22837
Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 2909dafc9
Time (s): cpu = 00:00:35 ; elapsed = 00:00:28 . Memory (MB): peak = 2792.863 ; gain = 0.000 ; free physical = 605 ; free virtual = 22837
Number of Nodes with overlaps = 0
Phase 2.3 Update Timing
Phase 2.3 Update Timing | Checksum: 232ab0f83
Time (s): cpu = 00:00:40 ; elapsed = 00:00:29 . Memory (MB): peak = 2792.863 ; gain = 0.000 ; free physical = 613 ; free virtual = 22845
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.996 | TNS=0.000 | WHS=-0.066 | THS=-0.066 |
Router Utilization Summary
Global Vertical Routing Utilization = 0 %
Global Horizontal Routing Utilization = 7.10429e-05 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 4525
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 4524
Number of Partially Routed Nets = 1
Number of Node Overlaps = 0
Phase 2 Router Initialization | Checksum: 2f3244bc6
Time (s): cpu = 00:00:42 ; elapsed = 00:00:30 . Memory (MB): peak = 2792.863 ; gain = 0.000 ; free physical = 613 ; free virtual = 22845
Phase 3 Initial Routing
Phase 3.1 Global Routing
Phase 3.1 Global Routing | Checksum: 2f3244bc6
Time (s): cpu = 00:00:42 ; elapsed = 00:00:30 . Memory (MB): peak = 2792.863 ; gain = 0.000 ; free physical = 613 ; free virtual = 22845
Phase 3.2 Initial Net Routing
Phase 3.2 Initial Net Routing | Checksum: 3233ade66
Time (s): cpu = 00:00:44 ; elapsed = 00:00:30 . Memory (MB): peak = 2792.863 ; gain = 0.000 ; free physical = 613 ; free virtual = 22845
Phase 3 Initial Routing | Checksum: 3233ade66
Time (s): cpu = 00:00:44 ; elapsed = 00:00:30 . Memory (MB): peak = 2792.863 ; gain = 0.000 ; free physical = 613 ; free virtual = 22845
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
Number of Nodes with overlaps = 540
Number of Nodes with overlaps = 2
Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.988 | TNS=0.000 | WHS=N/A | THS=N/A |
Phase 4.1 Global Iteration 0 | Checksum: 2d9840c8c
Time (s): cpu = 00:00:47 ; elapsed = 00:00:32 . Memory (MB): peak = 2792.863 ; gain = 0.000 ; free physical = 589 ; free virtual = 22821
Phase 4 Rip-up And Reroute | Checksum: 2d9840c8c
Time (s): cpu = 00:00:47 ; elapsed = 00:00:32 . Memory (MB): peak = 2792.863 ; gain = 0.000 ; free physical = 588 ; free virtual = 22820
Phase 5 Delay and Skew Optimization
Phase 5.1 Delay CleanUp
Phase 5.1 Delay CleanUp | Checksum: 2d9840c8c
Time (s): cpu = 00:00:47 ; elapsed = 00:00:32 . Memory (MB): peak = 2792.863 ; gain = 0.000 ; free physical = 588 ; free virtual = 22820
Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 2d9840c8c
Time (s): cpu = 00:00:47 ; elapsed = 00:00:32 . Memory (MB): peak = 2792.863 ; gain = 0.000 ; free physical = 588 ; free virtual = 22820
Phase 5 Delay and Skew Optimization | Checksum: 2d9840c8c
Time (s): cpu = 00:00:47 ; elapsed = 00:00:32 . Memory (MB): peak = 2792.863 ; gain = 0.000 ; free physical = 587 ; free virtual = 22819
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 2b2faecfc
Time (s): cpu = 00:00:47 ; elapsed = 00:00:32 . Memory (MB): peak = 2792.863 ; gain = 0.000 ; free physical = 602 ; free virtual = 22834
INFO: [Route 35-416] Intermediate Timing Summary | WNS=9.084 | TNS=0.000 | WHS=0.194 | THS=0.000 |
Phase 6.1 Hold Fix Iter | Checksum: 2b2faecfc
Time (s): cpu = 00:00:47 ; elapsed = 00:00:32 . Memory (MB): peak = 2792.863 ; gain = 0.000 ; free physical = 602 ; free virtual = 22834
Phase 6 Post Hold Fix | Checksum: 2b2faecfc
Time (s): cpu = 00:00:47 ; elapsed = 00:00:32 . Memory (MB): peak = 2792.863 ; gain = 0.000 ; free physical = 602 ; free virtual = 22834
Phase 7 Route finalize
Router Utilization Summary
Global Vertical Routing Utilization = 0.856378 %
Global Horizontal Routing Utilization = 1.08937 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 0
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 0
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
Phase 7 Route finalize | Checksum: 2b2faecfc
Time (s): cpu = 00:00:47 ; elapsed = 00:00:32 . Memory (MB): peak = 2792.863 ; gain = 0.000 ; free physical = 602 ; free virtual = 22834
Phase 8 Verifying routed nets
Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 2b2faecfc
Time (s): cpu = 00:00:47 ; elapsed = 00:00:32 . Memory (MB): peak = 2792.863 ; gain = 0.000 ; free physical = 602 ; free virtual = 22834
Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 248bd5899
Time (s): cpu = 00:00:48 ; elapsed = 00:00:32 . Memory (MB): peak = 2792.863 ; gain = 0.000 ; free physical = 602 ; free virtual = 22834
Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=9.084 | TNS=0.000 | WHS=0.194 | THS=0.000 |
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 10 Post Router Timing | Checksum: 248bd5899
Time (s): cpu = 00:00:48 ; elapsed = 00:00:32 . Memory (MB): peak = 2792.863 ; gain = 0.000 ; free physical = 602 ; free virtual = 22834
INFO: [Route 35-16] Router Completed Successfully
Phase 11 Post-Route Event Processing
Phase 11 Post-Route Event Processing | Checksum: d9bdebff
Time (s): cpu = 00:00:48 ; elapsed = 00:00:32 . Memory (MB): peak = 2792.863 ; gain = 0.000 ; free physical = 602 ; free virtual = 22834
Ending Routing Task | Checksum: d9bdebff
Time (s): cpu = 00:00:49 ; elapsed = 00:00:32 . Memory (MB): peak = 2792.863 ; gain = 0.000 ; free physical = 602 ; free virtual = 22834
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
12 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:51 ; elapsed = 00:00:33 . Memory (MB): peak = 2792.863 ; gain = 0.000 ; free physical = 602 ; free virtual = 22834
# report_timing_summary -no_header -no_detailed_paths
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
WARN (PR1014) : Generic routing resource will be used to clock signal 'clk_d' by the specified constraint. And then it may lead to the excessive delay or skew
[90%] Routing Phase 3 completed
Running timing analysis......
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------
Enable Multi Corner Analysis : Yes
Enable Pessimism Removal : Yes
Pessimism Removal Resolution : Nearest Common Node
Enable Input Delay Default Clock : No
Enable Preset / Clear Arcs : No
Disable Flight Delays : No
Ignore I/O Paths : No
Timing Early Launch at Borrowing Latches : No
Borrow Time for Max Delay Exceptions : Yes
Merge Timing Exceptions : Yes
Inter-SLR Compensation : Conservative
Corner Analyze Analyze
Name Max Paths Min Paths
------ --------- ---------
Slow Yes Yes
Fast Yes Yes
------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------
No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations.
check_timing report
Table of Contents
-----------------
1. checking no_clock (2552)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (8222)
5. checking no_input_delay (10)
6. checking no_output_delay (17)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)
1. checking no_clock (2552)
---------------------------
There are 2552 register/latch pins with no clock driven by root clock pin: clk_o_reg/Q (HIGH)
2. checking constant_clock (0)
------------------------------
There are 0 register/latch pins with constant_clock.
3. checking pulse_width_clock (0)
---------------------------------
There are 0 register/latch pins which need pulse_width check
4. checking unconstrained_internal_endpoints (8222)
---------------------------------------------------
There are 8222 pins that are not constrained for maximum delay. (HIGH)
There are 0 pins that are not constrained for maximum delay due to constant clock.
5. checking no_input_delay (10)
-------------------------------
There are 10 input ports with no input delay specified. (HIGH)
There are 0 input ports with no input delay but user has a false path constraint.
6. checking no_output_delay (17)
--------------------------------
There are 17 ports with no output delay specified. (HIGH)
There are 0 ports with no output delay but user has a false path constraint
There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
7. checking multiple_clock (0)
------------------------------
There are 0 register/latch pins with multiple clocks.
8. checking generated_clocks (0)
--------------------------------
There are 0 generated clocks that are not connected to a clock source.
9. checking loops (0)
---------------------
There are 0 combinational loops in the design.
10. checking partial_input_delay (0)
------------------------------------
There are 0 input ports with partial input delay specified.
11. checking partial_output_delay (0)
-------------------------------------
There are 0 ports with partial output delay specified.
12. checking latch_loops (0)
----------------------------
There are 0 combinational latch loops in the design through latch input
------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------
WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
9.109 0.000 0 1 0.210 0.000 0 1 4.500 0.000 0 3
All user specified timing constraints are met.
------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------
Clock Waveform(ns) Period(ns) Frequency(MHz)
----- ------------ ---------- --------------
sys_clk_pin {0.000 5.000} 10.000 100.000
------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------
Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
sys_clk_pin 9.109 0.000 0 1 0.210 0.000 0 1 4.500 0.000 0 3
------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------
From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
# report_route_status -file digilent_nexys4ddr_route_status.rpt
# report_drc -file digilent_nexys4ddr_drc.rpt
Command: report_drc -file digilent_nexys4ddr_drc.rpt
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/eda/vivado/Vivado/2023.2/data/ip'.
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4ddr_drc.rpt.
report_drc completed successfully
# report_timing_summary -datasheet -max_paths 10 -file digilent_nexys4ddr_timing.rpt
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
[95%] Timing analysis completed
Placement and routing completed
Bitstream generation in progress......
# report_power -file digilent_nexys4ddr_power.rpt
Command: report_power -file digilent_nexys4ddr_power.rpt
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
0 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
# write_bitstream -force "./build/out.bit"
Command: write_bitstream -force ./build/out.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
Bitstream generation completed
Running power analysis......
[100%] Power analysis completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.power.html" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.pin.html" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.rpt.html" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.rpt.txt" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.tr.html" completed
Wed Aug 28 02:07:21 2024
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
INFO: [DRC 23-27] Running DRC with 8 threads
WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND
set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0
Refer to the device configuration user guide for more information.
WARNING: [DRC DPOP-1] PREG Output pipelining: DSP SOC/Core/Mdu/acumulador0 output SOC/Core/Mdu/acumulador0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
WARNING: [DRC DPOP-1] PREG Output pipelining: DSP SOC/Core/Mdu/acumulador0__0 output SOC/Core/Mdu/acumulador0__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
WARNING: [DRC DPOP-2] MREG Output pipelining: DSP SOC/Core/Mdu/acumulador0 multiplier stage SOC/Core/Mdu/acumulador0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
WARNING: [DRC DPOP-2] MREG Output pipelining: DSP SOC/Core/Mdu/acumulador0__0 multiplier stage SOC/Core/Mdu/acumulador0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
WARNING: [DRC DPOP-2] MREG Output pipelining: DSP SOC/Core/Mdu/acumulador_reg multiplier stage SOC/Core/Mdu/acumulador_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
WARNING: [DRC DPOP-2] MREG Output pipelining: DSP SOC/Core/Mdu/acumulador_reg__0 multiplier stage SOC/Core/Mdu/acumulador_reg__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 7 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Writing bitstream ./build/out.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-83] Releasing license: Implementation
9 Infos, 7 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 3109.988 ; gain = 245.207 ; free physical = 601 ; free virtual = 22846
INFO: [Common 17-206] Exiting Vivado at Wed Aug 28 02:07:36 2024...
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Flash)
[Pipeline] parallel
[Pipeline] { (Branch: openFPGAloader ECP5)
[Pipeline] { (Branch: openFPGAloader Tangnano 20k)
[Pipeline] { (Branch: openFPGAloader Nexys 4 DDR)
[Pipeline] stage
[Pipeline] { (openFPGAloader ECP5)
[Pipeline] stage
[Pipeline] { (openFPGAloader Tangnano 20k)
[Pipeline] stage
[Pipeline] { (openFPGAloader Nexys 4 DDR)
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [Resource: ecp5]
Resource [ecp5] did not exist. Created.
Lock acquired on [Resource: ecp5]
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [Resource: tangnano20k]
Resource [tangnano20k] did not exist. Created.
Lock acquired on [Resource: tangnano20k]
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [Resource: nexys4]
Resource [nexys4] did not exist. Created.
Lock acquired on [Resource: nexys4]
[Pipeline] {
[Pipeline] echo
FPGA ECP5 Broqueada
[Pipeline] sh
[Pipeline] echo
FPGA TangNano Broqueada
+ /eda/oss-cad-suite/bin/openFPGALoader -b colorlight-i9 ./build/out.bit
empty
Found 1 compatible device:
0x0d28 0x0204 0x3 DAPLink CMSIS-DAP
Open file: DONE
b3bdffff
Parse file: DONE
Enable configuration: DONE
SRAM erase: DONE
[Pipeline] sh
[Pipeline] echo
FPGA Nexys 4 Broqueada
+ echo gravando na tang nano
gravando na tang nano
[Pipeline] sh
[Pipeline] }
+ cd Risco-5/fpga/nexys4_ddr
+ /eda/oss-cad-suite/bin/openFPGALoader -b nexys_a7_100 ./build/out.bit
empty
Jtag frequency : requested 6.00MHz -> real 6.00MHz
Open file DONE
Parse file DONE
load program
Lock released on resource [Resource: tangnano20k]
Loading: [===== ] 9.30%[Pipeline] // lock
[Pipeline] }
Load SRAM: [========= ] 18.00%[Pipeline] // script
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Loading: [========== ] 18.60%
Load SRAM: [=================== ] 38.00%
Loading: [============== ] 27.90%
Load SRAM: [============================= ] 58.00%
Loading: [=================== ] 37.21%
Load SRAM: [======================================= ] 78.00%
Loading: [======================== ] 46.51%
Load SRAM: [================================================= ] 98.00%
Load SRAM: [===================================================] 100.00%
Done
Shift IR 35
ir: 1 isc_done 1 isc_ena 0 init 1 done 1
[Pipeline] }
Loading: [============================ ] 55.81%Lock released on resource [Resource: nexys4]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // script
[Pipeline] }
[Pipeline] // stage
Loading: [================================= ] 65.11%[Pipeline] }
Loading: [====================================== ] 74.41%
Loading: [========================================== ] 83.71%
Loading: [=============================================== ] 93.01%
Loading: [==================================================] 100.00%
Done
Disable configuration: DONE
[Pipeline] }
Lock released on resource [Resource: ecp5]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // script
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Testes)
[Pipeline] parallel
[Pipeline] { (Branch: ECP5 - Testes)
[Pipeline] { (Branch: TangNano - Testes)
[Pipeline] { (Branch: Nexys 4 - Testes)
[Pipeline] stage
[Pipeline] { (ECP5 - Testes)
[Pipeline] stage
[Pipeline] { (TangNano - Testes)
[Pipeline] stage
[Pipeline] { (Nexys 4 - Testes)
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] echo
Rodando teste na ECP5
[Pipeline] lock
Trying to acquire lock on [Resource: ecp5]
Resource [ecp5] did not exist. Created.
Lock acquired on [Resource: ecp5]
[Pipeline] {
[Pipeline] echo
Rodando teste na tang nano
[Pipeline] lock
Trying to acquire lock on [Resource: tangnano20k]
Resource [tangnano20k] did not exist. Created.
Lock acquired on [Resource: tangnano20k]
[Pipeline] {
[Pipeline] echo
Rodando teste na Nexys 4
[Pipeline] lock
Trying to acquire lock on [Resource: nexys4]
Resource [nexys4] did not exist. Created.
Lock acquired on [Resource: nexys4]
[Pipeline] {
[Pipeline] echo
FPGA ECP5 Broqueada
[Pipeline] sh
[Pipeline] echo
FPGA TangNano Broqueada
+ echo testando na ecp5
testando na ecp5
[Pipeline] sh
[Pipeline] echo
FPGA Nexys 4 Broqueada
+ echo testando na tang nano
testando na tang nano
[Pipeline] sh
+ echo testando na tang nano
testando na tang nano
[Pipeline] }
Lock released on resource [Resource: ecp5]
[Pipeline] }
Lock released on resource [Resource: tangnano20k]
[Pipeline] // lock
[Pipeline] // lock
[Pipeline] echo
ECP5 liberada
[Pipeline] }
[Pipeline] echo
TangNano liberada
[Pipeline] }
[Pipeline] }
Lock released on resource [Resource: nexys4]
[Pipeline] // script
[Pipeline] // script
[Pipeline] // lock
[Pipeline] }
[Pipeline] }
[Pipeline] echo
TangNano liberada
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] // script
[Pipeline] }
[Pipeline] }
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
Finished: SUCCESS
![[Jenkins]](/jenkins/static/d05f6cb3/images/svgs/logo.svg){kind=logo}
