Console Output

+ cd Risco-5/fpga/nexys4_ddr
+ /eda/oss-cad-suite/bin/openFPGALoader -b nexys_a7_100 ./build/out.bit
empty
Jtag frequency : requested 6.00MHz   -> real 6.00MHz  
Open file DONE
Parse file DONE
load program

Load SRAM: [=========                                         ] 18.00%
Load SRAM: [===================                               ] 38.00%
Load SRAM: [=============================                     ] 58.00%
Load SRAM: [=======================================           ] 78.00%
Load SRAM: [================================================= ] 98.00%
Load SRAM: [===================================================] 100.00%
Done
Shift IR 35
ir: 1 isc_done 1 isc_ena 0 init 1 done 1