Console Output
+ /eda/oss-cad-suite/bin/nextpnr-ecp5 --json ./build/out.json --write ./build/out_pnr.json --45k --lpf Risco-5/fpga/ecp5/pinout.lpf --textcfg ./build/out.config --package CABGA381 --speed 6 --lpf-allow-unconstrained
Info: constraining clock net 'clk' to 25.00 MHz
Info: Logic utilisation before packing:
Info: Total LUT4s: 9741/43848 22%
Info: logic LUTs: 5631/43848 12%
Info: carry LUTs: 726/43848 1%
Info: RAM LUTs: 2256/ 5481 41%
Info: RAMW LUTs: 1128/10962 10%
Info: Total DFFs: 1216/43848 2%
Info: Packing IOs..
Info: $gpios[5]$iobuf_i: gpios_$_TBUF__Y.Y
Info: pin 'gpios[5]$tr_io' constrained to Bel 'X9/Y71/PIOB'.
Info: $gpios[4]$iobuf_i: gpios_$_TBUF__Y_1.Y
Info: pin 'gpios[4]$tr_io' constrained to Bel 'X4/Y71/PIOB'.
Info: $gpios[3]$iobuf_i: gpios_$_TBUF__Y_2.Y
Info: pin 'gpios[3]$tr_io' constrained to Bel 'X0/Y65/PIOB'.
Info: $gpios[2]$iobuf_i: gpios_$_TBUF__Y_3.Y
Info: pin 'gpios[2]$tr_io' constrained to Bel 'X9/Y71/PIOA'.
Info: $gpios[1]$iobuf_i: gpios_$_TBUF__Y_4.Y
Info: pin 'gpios[1]$tr_io' constrained to Bel 'X6/Y71/PIOA'.
Info: $gpios[0]$iobuf_i: gpios_$_TBUF__Y_5.Y
Info: pin 'gpios[0]$tr_io' constrained to Bel 'X4/Y71/PIOA'.
Info: pin 'tx$tr_io' constrained to Bel 'X90/Y20/PIOC'.
Info: pin 'rx$tr_io' constrained to Bel 'X90/Y20/PIOA'.
Info: pin 'reset$tr_io' constrained to Bel 'X0/Y29/PIOA'.
Info: pin 'led[7]$tr_io' constrained to Bel 'X90/Y20/PIOD'.
Info: pin 'led[6]$tr_io' constrained to Bel 'X0/Y44/PIOD'.
Info: pin 'led[5]$tr_io' constrained to Bel 'X0/Y59/PIOA'.
Info: pin 'led[4]$tr_io' constrained to Bel 'X15/Y71/PIOB'.
Info: pin 'led[3]$tr_io' constrained to Bel 'X90/Y29/PIOC'.
Info: pin 'led[2]$tr_io' constrained to Bel 'X90/Y44/PIOB'.
Info: pin 'led[1]$tr_io' constrained to Bel 'X0/Y44/PIOC'.
Info: pin 'led[0]$tr_io' constrained to Bel 'X0/Y59/PIOC'.
Info: pin 'clk$tr_io' constrained to Bel 'X0/Y68/PIOC'.
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 615 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info: promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0x300930cb
Info: Device utilisation:
Info: TRELLIS_IO: 18/ 245 7%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 4/ 72 5%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 0/ 4 0%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 1216/ 43848 2%
Info: TRELLIS_COMB: 9873/ 43848 22%
Info: TRELLIS_RAMW: 564/ 5481 10%
Info: Placed 18 cells based on constraints.
Info: Creating initial analytic placement for 4784 cells, random placement wirelen = 442280.
Info: at initial placer iter 0, wirelen = 2979
Info: at initial placer iter 1, wirelen = 2186
Info: at initial placer iter 2, wirelen = 2300
Info: at initial placer iter 3, wirelen = 2136
Info: Running main analytical placer, max placement attempts per cell = 17041122.
Info: at iteration #1, type ALL: wirelen solved = 2344, spread = 71183, legal = 69092; time = 0.30s
Info: at iteration #2, type ALL: wirelen solved = 7184, spread = 56496, legal = 58483; time = 0.29s
Info: at iteration #3, type ALL: wirelen solved = 10900, spread = 48500, legal = 51515; time = 0.29s
Info: at iteration #4, type ALL: wirelen solved = 13662, spread = 48705, legal = 50021; time = 0.29s
Info: at iteration #5, type ALL: wirelen solved = 16286, spread = 50060, legal = 51108; time = 0.41s
Info: at iteration #6, type ALL: wirelen solved = 18623, spread = 46900, legal = 47589; time = 0.31s
Info: at iteration #7, type ALL: wirelen solved = 18799, spread = 45743, legal = 46474; time = 0.27s
Info: at iteration #8, type ALL: wirelen solved = 20828, spread = 42860, legal = 43857; time = 0.27s
Info: at iteration #9, type ALL: wirelen solved = 21508, spread = 42072, legal = 43173; time = 0.27s
Info: at iteration #10, type ALL: wirelen solved = 21687, spread = 40728, legal = 41860; time = 0.27s
Info: at iteration #11, type ALL: wirelen solved = 21815, spread = 40738, legal = 41854; time = 0.34s
Info: at iteration #12, type ALL: wirelen solved = 23536, spread = 39938, legal = 41277; time = 0.32s
Info: at iteration #13, type ALL: wirelen solved = 24079, spread = 39488, legal = 40685; time = 0.27s
Info: at iteration #14, type ALL: wirelen solved = 24880, spread = 39282, legal = 40592; time = 0.27s
Info: at iteration #15, type ALL: wirelen solved = 25894, spread = 37801, legal = 39761; time = 0.27s
Info: at iteration #16, type ALL: wirelen solved = 25311, spread = 38063, legal = 39856; time = 0.28s
Info: at iteration #17, type ALL: wirelen solved = 25732, spread = 37450, legal = 39308; time = 0.27s
Info: at iteration #18, type ALL: wirelen solved = 26276, spread = 39216, legal = 40358; time = 0.32s
Info: at iteration #19, type ALL: wirelen solved = 27310, spread = 38908, legal = 40317; time = 0.37s
Info: at iteration #20, type ALL: wirelen solved = 27644, spread = 38304, legal = 39826; time = 0.26s
Info: at iteration #21, type ALL: wirelen solved = 27684, spread = 37601, legal = 39312; time = 0.26s
Info: at iteration #22, type ALL: wirelen solved = 27579, spread = 37477, legal = 39482; time = 0.26s
Info: HeAP Placer Time: 10.38s
Info: of which solving equations: 6.16s
Info: of which spreading cells: 0.81s
Info: of which strict legalisation: 0.28s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 6307, wirelen = 39308
Info: at iteration #5: temp = 0.000000, timing cost = 5352, wirelen = 34250
Info: at iteration #10: temp = 0.000000, timing cost = 4576, wirelen = 32985
Info: at iteration #15: temp = 0.000000, timing cost = 4946, wirelen = 32453
Info: at iteration #20: temp = 0.000000, timing cost = 4907, wirelen = 32249
Info: at iteration #25: temp = 0.000000, timing cost = 4782, wirelen = 32090
Info: at iteration #30: temp = 0.000000, timing cost = 4734, wirelen = 32048
Info: at iteration #30: temp = 0.000000, timing cost = 4714, wirelen = 32053
Info: SA placement time 40.26s
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 39.84 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 10.25 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 9.72 ns
Info: Slack histogram:
Info: legend: * represents 75 endpoint(s)
Info: + represents [1,75) endpoint(s)
Info: [ 14899, 16117) |+
Info: [ 16117, 17335) |+
Info: [ 17335, 18553) |+
Info: [ 18553, 19771) |+
Info: [ 19771, 20989) |****+
Info: [ 20989, 22207) |*************+
Info: [ 22207, 23425) |******+
Info: [ 23425, 24643) |***********+
Info: [ 24643, 25861) |*********+
Info: [ 25861, 27079) |*************+
Info: [ 27079, 28297) |********+
Info: [ 28297, 29515) |********+
Info: [ 29515, 30733) |************************************************************
Info: [ 30733, 31951) |*******************************************+
Info: [ 31951, 33169) |****+
Info: [ 33169, 34387) |*****+
Info: [ 34387, 35605) |**********+
Info: [ 35605, 36823) |********+
Info: [ 36823, 38041) |******+
Info: [ 38041, 39259) |***+
Info: Checksum: 0x98aa7179
Info: Routing globals...
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 47333 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 285 714 | 285 714 | 46725| 0.93 0.93|
Info: 2000 | 483 1516 | 198 802 | 45996| 0.34 1.27|
Info: 3000 | 632 2367 | 149 851 | 45247| 0.35 1.61|
Info: 4000 | 803 3196 | 171 829 | 44470| 0.33 1.94|
Info: 5000 | 934 4065 | 131 869 | 43644| 0.34 2.28|
Info: 6000 | 1087 4912 | 153 847 | 42986| 0.30 2.59|
Info: 7000 | 1228 5771 | 141 859 | 42264| 0.31 2.90|
Info: 8000 | 1361 6638 | 133 867 | 41551| 0.50 3.39|
Info: 9000 | 1551 7448 | 190 810 | 40947| 0.38 3.77|
Info: 10000 | 1675 8324 | 124 876 | 40287| 0.39 4.16|
Info: 11000 | 1853 9146 | 178 822 | 39605| 0.32 4.48|
Info: 12000 | 2071 9928 | 218 782 | 39007| 0.38 4.87|
Info: 13000 | 2242 10757 | 171 829 | 38308| 0.41 5.28|
Info: 14000 | 2469 11530 | 227 773 | 37632| 0.40 5.68|
Info: 15000 | 2657 12342 | 188 812 | 37147| 0.37 6.05|
Info: 16000 | 2866 13133 | 209 791 | 36424| 0.37 6.42|
Info: 17000 | 3027 13972 | 161 839 | 35974| 0.48 6.91|
Info: 18000 | 3196 14803 | 169 831 | 35650| 0.51 7.41|
Info: 19000 | 3419 15580 | 223 777 | 35036| 0.40 7.81|
Info: 20000 | 3656 16343 | 237 763 | 34409| 0.40 8.21|
Info: 21000 | 3841 17158 | 185 815 | 33833| 0.40 8.61|
Info: 22000 | 4085 17914 | 244 756 | 33219| 0.41 9.02|
Info: 23000 | 4288 18711 | 203 797 | 32584| 0.36 9.38|
Info: 24000 | 4502 19497 | 214 786 | 32006| 0.29 9.67|
Info: 25000 | 4713 20286 | 211 789 | 31324| 0.37 10.05|
Info: 26000 | 4911 21088 | 198 802 | 30586| 0.48 10.52|
Info: 27000 | 5150 21849 | 239 761 | 29923| 0.47 11.00|
Info: 28000 | 5340 22659 | 190 810 | 29284| 0.36 11.36|
Info: 29000 | 5587 23412 | 247 753 | 28742| 0.38 11.74|
Info: 30000 | 5828 24171 | 241 759 | 28061| 0.31 12.05|
Info: 31000 | 6003 24996 | 175 825 | 27438| 0.34 12.39|
Info: 32000 | 6225 25774 | 222 778 | 26763| 0.34 12.74|
Info: 33000 | 6495 26504 | 270 730 | 26127| 0.38 13.11|
Info: 34000 | 6778 27221 | 283 717 | 25559| 0.52 13.64|
Info: 35000 | 7073 27926 | 295 705 | 25004| 0.42 14.06|
Info: 36000 | 7339 28660 | 266 734 | 24429| 0.37 14.43|
Info: 37000 | 7675 29324 | 336 664 | 23914| 0.37 14.79|
Info: 38000 | 7975 30024 | 300 700 | 23688| 0.38 15.17|
Info: 39000 | 8248 30751 | 273 727 | 23195| 0.46 15.63|
Info: 40000 | 8533 31466 | 285 715 | 22658| 0.51 16.14|
Info: 41000 | 8874 32125 | 341 659 | 22189| 0.61 16.75|
Info: 42000 | 9192 32807 | 318 682 | 21873| 0.39 17.13|
Info: 43000 | 9477 33522 | 285 715 | 21589| 0.35 17.49|
Info: 44000 | 9832 34167 | 355 645 | 21062| 0.36 17.85|
Info: 45000 | 10220 34779 | 388 612 | 20594| 0.39 18.24|
Info: 46000 | 10636 35363 | 416 584 | 20187| 0.39 18.63|
Info: 47000 | 11043 35956 | 407 593 | 19936| 0.43 19.07|
Info: 48000 | 11408 36591 | 365 635 | 19631| 0.40 19.46|
Info: 49000 | 11775 37224 | 367 633 | 19234| 0.38 19.85|
Info: 50000 | 12183 37816 | 408 592 | 18848| 0.38 20.22|
Info: 51000 | 12591 38408 | 408 592 | 18446| 0.39 20.61|
Info: 52000 | 13027 38947 | 436 539 | 17977| 0.38 20.99|
Info: 53000 | 13449 39507 | 422 560 | 17504| 0.43 21.42|
Info: 54000 | 13830 40089 | 381 582 | 17689| 0.41 21.84|
Info: 55000 | 13992 40915 | 162 826 | 16971| 0.37 22.21|
Info: 56000 | 14271 41612 | 279 697 | 16783| 0.74 22.94|
Info: 57000 | 14597 42173 | 326 561 | 16162| 0.55 23.49|
Info: 58000 | 14854 42764 | 257 591 | 15463| 0.28 23.77|
Info: 59000 | 15068 43364 | 214 600 | 14720| 0.28 24.05|
Info: 60000 | 15342 43978 | 274 614 | 14066| 0.26 24.31|
Info: 61000 | 15576 44664 | 234 686 | 13332| 0.25 24.56|
Info: 62000 | 15777 45390 | 201 726 | 12630| 0.25 24.81|
Info: 63000 | 16006 46109 | 229 719 | 11889| 0.22 25.03|
Info: 64000 | 16295 46763 | 289 654 | 11196| 0.32 25.35|
Info: 65000 | 16709 47284 | 414 521 | 10656| 0.40 25.75|
Info: 66000 | 17035 47925 | 326 641 | 10006| 0.30 26.05|
Info: 67000 | 17257 48642 | 222 717 | 9343| 0.37 26.42|
Info: 68000 | 17313 49583 | 56 941 | 8405| 0.31 26.73|
Info: 69000 | 17326 50570 | 13 987 | 7420| 0.13 26.86|
Info: 70000 | 17336 51560 | 10 990 | 6431| 0.13 26.99|
Info: 71000 | 17349 52530 | 13 970 | 5444| 0.13 27.11|
Info: 72000 | 17376 53468 | 27 938 | 4471| 0.14 27.25|
Info: 73000 | 17450 54309 | 74 841 | 3558| 0.29 27.54|
Info: 74000 | 17549 55140 | 99 831 | 2665| 0.25 27.79|
Info: 75000 | 17616 55986 | 67 846 | 1751| 0.26 28.05|
Info: 76000 | 17688 56886 | 72 900 | 863| 0.27 28.32|
Info: 76873 | 17699 57311 | 11 425 | 0| 0.18 28.50|
Info: Routing complete.
Info: Router1 time 28.50s
Info: Checksum: 0xc2223912
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: curr total
Info: 0.5 0.5 Source SOC.Core.Control_Unit.state_TRELLIS_FF_Q.Q
Info: 2.1 2.7 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_3_A_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_LUT4_C_Z_LUT4_Z_B_L6MUX21_Z_SD[0] (31,17) -> (18,8)
Info: Sink SOC.Core.RegisterBank.registers.0.2_DO_LUT4_Z.C
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 2.9 Source SOC.Core.RegisterBank.registers.0.2_DO_LUT4_Z.F
Info: 2.0 4.9 Net SOC.Core.Control_Unit.nextstate_LUT4_Z_5_A_LUT4_Z_D_LUT4_Z_C_LUT4_Z_1_C[0] (18,8) -> (32,19)
Info: Sink SOC.Core.RegisterBank.registers.0.2_DO_3_LUT4_B_Z_LUT4_Z.C
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 5.1 Source SOC.Core.RegisterBank.registers.0.2_DO_3_LUT4_B_Z_LUT4_Z.F
Info: 1.3 6.4 Net SOC.Core.Control_Unit.nextstate_LUT4_Z_5_B_LUT4_D_Z_LUT4_Z_B_LUT4_Z_1_C_LUT4_Z_A[3] (32,19) -> (21,18)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_3_A_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_LUT4_C_Z_L6MUX21_Z_SD_LUT4_Z_1.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 6.7 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_3_A_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_LUT4_C_Z_L6MUX21_Z_SD_LUT4_Z_1.F
Info: 0.4 7.1 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_3_A_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_LUT4_C_Z_L6MUX21_Z_SD[5] (21,18) -> (21,18)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_3_A_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_LUT4_C_Z_L6MUX21_Z_SD_LUT4_C.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 7.3 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_3_A_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_LUT4_C_Z_L6MUX21_Z_SD_LUT4_C.OFX
Info: 1.4 8.8 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_3_A_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_LUT4_C_Z[1] (21,18) -> (25,14)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_3_A_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.B
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.4 9.2 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_3_A_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 9.2 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_3_A_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (25,14) -> (25,14)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_3_A_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 9.2 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_3_A_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 9.2 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_3_A_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (25,14) -> (25,14)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_3_A_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/src/core/alu.v:33.26-33.45
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 9.3 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_3_A_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 9.3 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_3_A_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (25,14) -> (25,14)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_3_A_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.4 9.7 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_3_A_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.F
Info: 0.6 10.3 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_3_A_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1[3] (25,14) -> (23,14)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_3_A_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_LUT4_C.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 10.6 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_3_A_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_LUT4_C.F
Info: 0.7 11.3 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_3_A_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_LUT4_C_Z[5] (23,14) -> (23,13)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_3_A_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_LUT4_C_Z_L6MUX21_SD_D1_PFUMX_Z_ALUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 11.5 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_3_A_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_LUT4_C_Z_L6MUX21_SD_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 1.3 12.8 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_3_A_LUT4_Z_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_LUT4_C_Z_L6MUX21_SD_Z[5] (23,13) -> (23,2)
Info: Sink SOC.Core.Alu.ALU_out_S_L6MUX21_Z_4_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 13.1 Source SOC.Core.Alu.ALU_out_S_L6MUX21_Z_4_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 0.0 13.1 Net SOC.Core.Alu.ALU_out_S_L6MUX21_Z_4_D1 (23,2) -> (23,2)
Info: Sink SOC.Core.Alu.ALU_out_S_L6MUX21_Z_4_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.70-157.72
Info: 0.2 13.3 Source SOC.Core.Alu.ALU_out_S_L6MUX21_Z_4_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 1.1 14.4 Net SOC.Core.alu_out[11] (23,2) -> (23,12)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_4_A_LUT4_C_Z_L6MUX21_SD_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.C
Info: Defined in:
Info: Risco-5/src/core/core.v:60.31-60.38
Info: 0.2 14.6 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_4_A_LUT4_C_Z_L6MUX21_SD_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.F
Info: 0.0 14.6 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_4_A_LUT4_C_Z_L6MUX21_SD_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT (23,12) -> (23,12)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_4_A_LUT4_C_Z_L6MUX21_SD_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.F1
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.46-157.48
Info: 0.2 14.8 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_4_A_LUT4_C_Z_L6MUX21_SD_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 0.0 14.8 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_4_A_LUT4_C_Z_L6MUX21_SD_Z_L6MUX21_Z_D1_L6MUX21_Z_D1 (23,12) -> (23,12)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_4_A_LUT4_C_Z_L6MUX21_SD_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.62-157.64
Info: 0.2 15.0 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_4_A_LUT4_C_Z_L6MUX21_SD_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 0.0 15.0 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_4_A_LUT4_C_Z_L6MUX21_SD_Z_L6MUX21_Z_D1 (23,12) -> (23,12)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_4_A_LUT4_C_Z_L6MUX21_SD_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.70-157.72
Info: 0.2 15.3 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_4_A_LUT4_C_Z_L6MUX21_SD_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 1.2 16.5 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_4_A_LUT4_C_Z_L6MUX21_SD_Z[4] (23,12) -> (30,14)
Info: Sink SOC.Core.Pc.load_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 16.7 Source SOC.Core.Pc.load_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 1.9 18.6 Net SOC.Core.pc_load (30,14) -> (19,4)
Info: Sink SOC.Core.Pc.Output_TRELLIS_FF_Q_18.CE
Info: Defined in:
Info: Risco-5/src/core/core.v:51.32-51.39
Info: 0.0 18.6 Setup SOC.Core.Pc.Output_TRELLIS_FF_Q_18.CE
Info: 4.5 ns logic, 14.1 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: curr total
Info: 0.0 0.0 Source gpios[5]$tr_io.O
Info: 2.9 2.9 Net gpios[5]$TRELLIS_IO_IN (9,71) -> (9,42)
Info: Sink SOC.GPIOS.Gpios[5].data_in_LUT4_B.A
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:7.16-7.21
Info: 0.2 3.1 Source SOC.GPIOS.Gpios[5].data_in_LUT4_B.F
Info: 1.0 4.1 Net SOC.GPIOS.Gpios[5].data_in_LUT4_B_Z[4] (9,42) -> (9,37)
Info: Sink SOC.GPIOS.Gpios[5].data_in_LUT4_B_Z_PFUMX_C0_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 4.4 Source SOC.GPIOS.Gpios[5].data_in_LUT4_B_Z_PFUMX_C0_BLUT_LUT4_Z.OFX
Info: 1.1 5.4 Net SOC.GPIOS.Gpios[5].data_in_LUT4_B_Z_PFUMX_C0_Z[1] (9,37) -> (12,32)
Info: Sink SOC.Core.read_data_LUT4_Z_4.B
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 5.7 Source SOC.Core.read_data_LUT4_Z_4.F
Info: 1.7 7.4 Net SOC.read_data[5] (12,32) -> (19,21)
Info: Sink SOC.Core.instruction_register_TRELLIS_FF_Q_25.M
Info: Defined in:
Info: Risco-5/src/peripheral/soc.v:24.34-24.43
Info: 0.0 7.4 Setup SOC.Core.instruction_register_TRELLIS_FF_Q_25.M
Info: 0.7 ns logic, 6.7 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: curr total
Info: 0.5 0.5 Source SOC.Leds.data_TRELLIS_FF_Q_29.Q
Info: 3.8 4.3 Net SOC.Leds.data[2] (23,27) -> (71,43)
Info: Sink led_LUT4_Z_6.D
Info: Defined in:
Info: Risco-5/src/peripheral/leds.v:19.12-19.16
Info: 0.2 4.5 Source led_LUT4_Z_6.F
Info: 1.7 6.2 Net led[2]$TRELLIS_IO_OUT (71,43) -> (90,44)
Info: Sink led[2]$tr_io.I
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:6.22-6.25
Info: 0.8 ns logic, 5.4 ns routing
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 53.64 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 7.38 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 6.19 ns
Info: Slack histogram:
Info: legend: * represents 84 endpoint(s)
Info: + represents [1,84) endpoint(s)
Info: [ 21358, 22243) |+
Info: [ 22243, 23128) |*+
Info: [ 23128, 24013) |*******+
Info: [ 24013, 24898) |**********+
Info: [ 24898, 25783) |**+
Info: [ 25783, 26668) |*+
Info: [ 26668, 27553) |***+
Info: [ 27553, 28438) |************+
Info: [ 28438, 29323) |*******************+
Info: [ 29323, 30208) |**+
Info: [ 30208, 31093) |+
Info: [ 31093, 31978) |*********+
Info: [ 31978, 32863) |************************************************************
Info: [ 32863, 33748) |********************************+
Info: [ 33748, 34633) |***+
Info: [ 34633, 35518) |**+
Info: [ 35518, 36403) |*******+
Info: [ 36403, 37288) |**********+
Info: [ 37288, 38173) |****+
Info: [ 38173, 39058) |***+
Info: Program finished normally.
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