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Start of Pipeline - (3 min 7 sec in block)
node - (3 min 6 sec in block)
node block - (3 min 5 sec in block)
stage - (3.9 sec in block)Git Clone
stage block (Git Clone) - (3.3 sec in block)
sh - (0.48 sec in self)rm -Rf Risco-5/ build/
sh - (2.2 sec in self)git clone https://github.com/JN513/Risco-5
sh - (0.4 sec in self)cd Risco-5
stage - (2.9 sec in block)IVerilog
stage block (IVerilog) - (2.4 sec in block)
sh - (0.45 sec in self)mkdir -p build
sh - (0.45 sec in self)cp Risco-5/software/memory/add.hex Risco-5/software/memory/generic.hex
sh - (0.48 sec in self) /eda/oss-cad-suite/bin/iverilog -o build/soc_test.o -s soc_tb -I Risco-5/src/ Risco-5/src/core/*.v Risco-5/src/peripheral/*.v Risco-5/tests/soc_test.v
sh - (0.45 sec in self)/eda/oss-cad-suite/bin/vvp build/soc_test.o
sh - (0.4 sec in self)rm -f Risco-5/software/memory/generic.hex
stage - (2 min 29 sec in block)Síntese
stage block (Síntese) - (2 min 28 sec in block)
parallel - (2 min 28 sec in block)
parallel block (Branch: OSS-Cad-Suite) - (57 ms in block)
stage - (1 min 47 sec in block)OSS-Cad-Suite
stage block (OSS-Cad-Suite) - (1 min 47 sec in block)
stage - (20 sec in block)Yosys
stage block (Yosys) - (20 sec in block)
sh - (19 sec in self) /eda/oss-cad-suite/bin/yosys -p " read_verilog Risco-5/fpga/ecp5/*.v; read_verilog Risco-5/debug/reset.v; read_verilog Risco-5/src/core/*.v; read_verilog Risco-5/src/peripheral/*.v; synth_ecp5 -json ./build/out.json -abc9 "
stage - (1 min 24 sec in block)NextPNR
stage block (NextPNR) - (1 min 23 sec in block)
sh - (1 min 23 sec in self) /eda/oss-cad-suite/bin/nextpnr-ecp5 --json ./build/out.json --write ./build/out_pnr.json --45k --lpf Risco-5/fpga/ecp5/pinout.lpf --textcfg ./build/out.config --package CABGA381 --speed 6 --lpf-allow-unconstrained
stage - (1.3 sec in block)ECPPACK
stage block (ECPPACK) - (1.1 sec in block)
sh - (0.91 sec in self)/eda/oss-cad-suite/bin/ecppack --compress --input ./build/out.config --bit ./build/out.bit
parallel block (Branch: Gowin) - (56 ms in block)
stage - (2 min 12 sec in block)Gowin
stage block (Gowin) - (2 min 11 sec in block)
sh - (0.73 sec in self)rm -rf Risco-5/impl/pnr
sh - (0.45 sec in self)mkdir -p Risco-5/impl/pnr
sh - (2 min 10 sec in self)cd Risco-5/fpga/tangnano20k/ && /eda/gowin/IDE/bin/gw_sh run.tcl
parallel block (Branch: Vivado) - (2 min 27 sec in block)
stage - (2 min 26 sec in block)Vivado
stage block (Vivado) - (2 min 26 sec in block)
sh - (2 min 26 sec in self)cd Risco-5/fpga/nexys4_ddr && mkdir build && /eda/vivado/Vivado/2023.2/bin/vivado -mode batch -nolog -nojournal -source run.tcl
stage - (17 sec in block)FPGA Flash
stage block (FPGA Flash) - (16 sec in block)
parallel - (16 sec in block)
parallel block (Branch: openFPGAloader ECP5) - (56 ms in block)
stage - (15 sec in block)openFPGAloader ECP5
stage block (openFPGAloader ECP5) - (15 sec in block)
script - (14 sec in block)
script block - (14 sec in block)
lock - (13 sec in block)ecp5
lock block - (12 sec in block)
echo - (0.16 sec in self)FPGA ECP5 Broqueada
sh - (11 sec in self)/eda/oss-cad-suite/bin/openFPGALoader -b colorlight-i9 ./build/out.bit
parallel block (Branch: openFPGAloader Tangnano 20k) - (56 ms in block)
stage - (4.6 sec in block)openFPGAloader Tangnano 20k
stage block (openFPGAloader Tangnano 20k) - (4.4 sec in block)
script - (3.6 sec in block)
script block - (3.3 sec in block)
lock - (2.4 sec in block)tangnano20k
lock block - (1.7 sec in block)
echo - (0.16 sec in self)FPGA TangNano Broqueada
sh - (0.6 sec in self)echo "gravando na tang nano"
parallel block (Branch: openFPGAloader Nexys 4 DDR) - (10 sec in block)
stage - (9.6 sec in block)openFPGAloader Nexys 4 DDR
stage block (openFPGAloader Nexys 4 DDR) - (9.3 sec in block)
script - (8.7 sec in block)
script block - (8.5 sec in block)
lock - (7.2 sec in block)nexys4
lock block - (6.6 sec in block)
echo - (0.14 sec in self)FPGA Nexys 4 Broqueada
sh - (5.6 sec in self)cd Risco-5/fpga/nexys4_ddr && /eda/oss-cad-suite/bin/openFPGALoader -b nexys_a7_100 ./build/out.bit
stage - (11 sec in block)Testes
stage block (Testes) - (11 sec in block)
parallel - (10 sec in block)
parallel block (Branch: ECP5 - Testes) - (56 ms in block)
stage - (8.5 sec in block)ECP5 - Testes
stage block (ECP5 - Testes) - (7.9 sec in block)
script - (6.5 sec in block)
script block - (5.3 sec in block)
echo - (0.22 sec in self)Rodando teste na ECP5
lock - (4.4 sec in block)ecp5
lock block - (2.5 sec in block)
echo - (0.16 sec in self)FPGA ECP5 Broqueada
sh - (1 sec in self)echo "testando na ecp5"
echo - (0.22 sec in self)ECP5 liberada
parallel block (Branch: TangNano - Testes) - (58 ms in block)
stage - (8.4 sec in block)TangNano - Testes
stage block (TangNano - Testes) - (7.8 sec in block)
script - (6.5 sec in block)
script block - (5.6 sec in block)
echo - (0.22 sec in self)Rodando teste na tang nano
lock - (4.2 sec in block)tangnano20k
lock block - (2.3 sec in block)
echo - (0.16 sec in self)FPGA TangNano Broqueada
sh - (1 sec in self)echo "testando na tang nano"
echo - (0.22 sec in self)TangNano liberada
parallel block (Branch: Nexys 4 - Testes) - (9.8 sec in block)
stage - (8.9 sec in block)Nexys 4 - Testes
stage block (Nexys 4 - Testes) - (8.5 sec in block)
script - (7.7 sec in block)
script block - (7.2 sec in block)
echo - (0.22 sec in self)Rodando teste na Nexys 4
lock - (5.4 sec in block)nexys4
lock block - (3.6 sec in block)
echo - (0.16 sec in self)FPGA Nexys 4 Broqueada
sh - (2.6 sec in self)echo "testando na tang nano"
echo - (0.11 sec in self)TangNano liberada