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Start of Pipeline - (25 sec in block)
node - (24 sec in block)
node block - (24 sec in block)
stage - (13 sec in block)Git Clone
stage block (Git Clone) - (13 sec in block)
sh - (0.46 sec in self)rm -rf *.xml
sh - (0.46 sec in self)rm -rf Rift2Core
sh - (12 sec in self)git clone --recursive --depth=1 https://github.com/whutddk/Rift2Core Rift2Core
stage - (1.4 sec in block)Simulation
stage block (Simulation) - (0.96 sec in block)
dir - (0.57 sec in block)Rift2Core
dir block - (0.31 sec in block)
echo - (0.1 sec in self)simulation not supported for mixed VHDL and Verilog files
stage - (2 sec in block)Utilities
stage block (Utilities) - (1.4 sec in block)
dir - (0.99 sec in block)Rift2Core
dir block - (0.69 sec in block)
sh - (0.46 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config -o /jenkins/processor_ci_utils/labels
stage - (5.6 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (5 sec in block)
getContext - (0.26 sec in self)
parallel - (4.4 sec in block)
parallel block (Branch: digilent_arty_a7_100t) - (4 sec in block)
stage - (3.6 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (3.3 sec in block)
getContext - (0.38 sec in self)
stage - (0.94 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (0.35 sec in block)
getContext - (0.15 sec in self)
stage - (1 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (0.43 sec in block)
getContext - (0.15 sec in self)
stage - (0.66 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (0.35 sec in block)
getContext - (0.16 sec in self)
stage - (0.75 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.51 sec in block)
junit - (0.25 sec in self)**/*.xml