Skip to content
[Jenkins]Jenkins
log in
StepArgumentsStatus
Start of Pipeline - (13 sec in block)
node - (13 sec in block)
node block - (12 sec in block)
stage - (2.8 sec in block)Git Clone
stage block (Git Clone) - (2.3 sec in block)
sh - (0.46 sec in self)rm -rf *.xml
sh - (0.44 sec in self)rm -rf RV32IC-CPU
sh - (1.2 sec in self)git clone --recursive --depth=1 https://github.com/djzenma/RV32IC-CPU RV32IC-CPU
stage - (2 sec in block)Simulation
stage block (Simulation) - (1.4 sec in block)
dir - (0.97 sec in block)RV32IC-CPU
dir block - (0.65 sec in block)
sh - (0.45 sec in self)/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s RISCV_TOP RTL/Adder.v RTL/CSRRegFile.v RTL/ClkInverter.v RTL/InterruptAddressGenerator.v RTL/Interrupt_Detector.v RTL/PIC.v RTL/RISCV.v RTL/RISCV_TOP.v RTL/RegSrcUnit.v RTL/TMRGenerator.v RTL/decompression.v RTL/memAddressSelectUnit.v RTL/ALU/ALU.v RTL/ALU/AdderSub.v RTL/ALU/Full_Adder.v RTL/ALU/RippleAdder.v RTL/Control/ALUControl.v RTL/Control/BranchUnit.v RTL/Control/ControlUnit.v RTL/Global/values.v RTL/Memory/Memory.v RTL/Other Units/ClkDiv.v RTL/Other Units/ForwardUnit.v RTL/Other Units/ImmGen.v RTL/Others/Decoder5_32.v RTL/Others/Mux2_1.v RTL/Others/Mux4_1.v RTL/Others/SSDDriver.v RTL/Others/ShiftLeft1.v RTL/Others/SignExtend.v RTL/Registers/FlipFlop.v RTL/Registers/RegFile.v RTL/Registers/RegWLoad.v RTL/Registers/regfileModel.v
stage - (0.95 sec in block)Utilities
stage block (Utilities) - (0.35 sec in block)
getContext - (0.15 sec in self)
stage - (5.6 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (5 sec in block)
getContext - (0.28 sec in self)
parallel - (4.3 sec in block)
parallel block (Branch: digilent_arty_a7_100t) - (4 sec in block)
stage - (3.5 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (3.3 sec in block)
getContext - (0.37 sec in self)
stage - (0.95 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (0.38 sec in block)
getContext - (0.17 sec in self)
stage - (0.92 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (0.36 sec in block)
getContext - (0.15 sec in self)
stage - (0.66 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (0.35 sec in block)
getContext - (0.16 sec in self)
stage - (0.76 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.51 sec in block)
junit - (0.28 sec in self)**/*.xml