Console Output

Started by timer
[Pipeline] Start of Pipeline
[Pipeline] node
Running on Jenkins in /var/jenkins_home/workspace/RV12
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone)
[Pipeline] sh
+ rm -rf *.xml
[Pipeline] sh
+ rm -rf RV12
[Pipeline] sh
+ git clone --recursive --depth=1 https://github.com/roalogic/RV12 RV12
Cloning into 'RV12'...
Submodule 'submodules/ahb3lite_pkg' (https://github.com/RoaLogic/ahb3lite_pkg.git) registered for path 'submodules/ahb3lite_pkg'
Submodule 'submodules/memory' (https://github.com/RoaLogic/memory.git) registered for path 'submodules/memory'
Cloning into '/var/jenkins_home/workspace/RV12/RV12/submodules/ahb3lite_pkg'...
Cloning into '/var/jenkins_home/workspace/RV12/RV12/submodules/memory'...
Submodule path 'submodules/ahb3lite_pkg': checked out '75e75f521f8c34afdc1db1ea9d5be64bffbfe11c'
Submodule path 'submodules/memory': checked out '4c4de0068f8f09189812ce510e986b86e11b99fa'
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Simulation)
[Pipeline] dir
Running in /var/jenkins_home/workspace/RV12/RV12
[Pipeline] {
[Pipeline] echo
simulation not supported for System Verilog files
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Utilities)
[Pipeline] dir
Running in /var/jenkins_home/workspace/RV12/RV12
[Pipeline] {
[Pipeline] sh
+ pwd
+ python3 /eda/processor_ci/core/labeler_prototype.py -d /var/jenkins_home/workspace/RV12/RV12 -c /eda/processor_ci/config -o /jenkins/processor_ci_utils/labels
Trying to read file: /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/ahb3lite/riscv_top_ahb3lite.sv
Trying to read file: /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/ahb3lite/biu_ahb3lite.sv
Trying to read file: /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/ahb3lite/riscv_top_ahb3lite.sv
Trying to read file: /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/core/riscv_bp.sv
Trying to read file: /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/core/riscv_core.sv
Trying to read file: /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/core/riscv_du.sv
Cache-related signals in biu_ahb3lite.sv
Possible cache file: riscv_cache_pkg.sv
Cache-related signals in riscv_cache_pkg.sv
Cache-related signals in riscv_id.sv
Cache-related signals in riscv_parcel_queue.sv
Cache-related signals in riscv_if.sv
Cache-related signals in riscv_imem_ctrl.sv
Cache-related signals in riscv_wbuf.sv
Cache-related signals in riscv_dmem_ctrl.sv
Possible cache file: riscv_nodcache_core.sv
Possible cache file: riscv_cache_setup.sv
Possible cache file: riscv_cache_tag.sv
Cache-related signals in riscv_cache_tag.sv
Possible cache file: riscv_noicache_core.sv
Possible cache file: riscv_cache_biu_ctrl.sv
Cache-related signals in riscv_cache_biu_ctrl.sv
Possible cache file: riscv_icache_core.sv
Cache-related signals in riscv_icache_core.sv
Possible cache file: riscv_cache_memory.sv
Cache-related signals in riscv_cache_memory.sv
Possible cache file: riscv_dcache_core.sv
Cache-related signals in riscv_dcache_core.sv
Possible cache file: riscv_dcache_fsm.sv
Cache-related signals in riscv_dcache_fsm.sv
Possible cache file: riscv_icache_fsm.sv
Cache-related signals in riscv_icache_fsm.sv
Cache-related signals in ahb3lite_pkg.sv
Results saved to /jenkins/processor_ci_utils/labels/RV12.json
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Build Pipeline)
[Pipeline] parallel
[Pipeline] { (Branch: digilent_arty_a7_100t)
[Pipeline] stage
[Pipeline] { (digilent_arty_a7_100t)
[Pipeline] lock
Trying to acquire lock on [Resource: digilent_arty_a7_100t]
Resource [digilent_arty_a7_100t] did not exist. Created.
Lock acquired on [Resource: digilent_arty_a7_100t]
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Synthesis and PnR)
[Pipeline] dir
Running in /var/jenkins_home/workspace/RV12/RV12
[Pipeline] {
[Pipeline] echo
Starting synthesis for FPGA digilent_arty_a7_100t.
[Pipeline] sh
+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p RV12 -b digilent_arty_a7_100t
[LOCK] Criado: run.lock
File 'processor_ci_defines.vh' generated for board: 'digilent_arty_a7_100t'.
Final configuration file generated at /var/jenkins_home/workspace/RV12/RV12/build_digilent_arty_a7_100t.tcl
[LOCK] Removido: run.lock
Error executing Makefile.
ERROR: [Synth 8-36] 'ahb3lite_pkg' is not declared [/var/jenkins_home/workspace/RV12/RV12/rtl/verilog/ahb3lite/biu_ahb3lite.sv:48]
ERROR: [Synth 8-36] 'HSIZE_SIZE' is not declared [/var/jenkins_home/workspace/RV12/RV12/rtl/verilog/ahb3lite/biu_ahb3lite.sv:66]
ERROR: [Synth 8-9960] range must be bounded by constant expressions [/var/jenkins_home/workspace/RV12/RV12/rtl/verilog/ahb3lite/biu_ahb3lite.sv:66]
ERROR: [Synth 8-36] 'HBURST_SIZE' is not declared [/var/jenkins_home/workspace/RV12/RV12/rtl/verilog/ahb3lite/biu_ahb3lite.sv:67]
ERROR: [Synth 8-9960] range must be bounded by constant expressions [/var/jenkins_home/workspace/RV12/RV12/rtl/verilog/ahb3lite/biu_ahb3lite.sv:67]
ERROR: [Synth 8-36] 'HPROT_SIZE' is not declared [/var/jenkins_home/workspace/RV12/RV12/rtl/verilog/ahb3lite/biu_ahb3lite.sv:68]
ERROR: [Synth 8-9960] range must be bounded by constant expressions [/var/jenkins_home/workspace/RV12/RV12/rtl/verilog/ahb3lite/biu_ahb3lite.sv:68]
ERROR: [Synth 8-36] 'HTRANS_SIZE' is not declared [/var/jenkins_home/workspace/RV12/RV12/rtl/verilog/ahb3lite/biu_ahb3lite.sv:69]
ERROR: [Synth 8-9960] range must be bounded by constant expressions [/var/jenkins_home/workspace/RV12/RV12/rtl/verilog/ahb3lite/biu_ahb3lite.sv:69]
ERROR: [Synth 8-36] 'HSIZE_SIZE' is not declared [/var/jenkins_home/workspace/RV12/RV12/rtl/verilog/ahb3lite/biu_ahb3lite.sv:103]
ERROR: [Synth 8-9960] range must be bounded by constant expressions [/var/jenkins_home/workspace/RV12/RV12/rtl/verilog/ahb3lite/biu_ahb3lite.sv:103]
ERROR: [Synth 8-36] 'HSIZE_BYTE' is not declared [/var/jenkins_home/workspace/RV12/RV12/rtl/verilog/ahb3lite/biu_ahb3lite.sv:107]
ERROR: [Synth 8-36] 'HSIZE_HWORD' is not declared [/var/jenkins_home/workspace/RV12/RV12/rtl/verilog/ahb3lite/biu_ahb3lite.sv:108]
ERROR: [Synth 8-36] 'HSIZE_WORD' is not declared [/var/jenkins_home/workspace/RV12/RV12/rtl/verilog/ahb3lite/biu_ahb3lite.sv:109]
ERROR: [Synth 8-36] 'HSIZE_DWORD' is not declared [/var/jenkins_home/workspace/RV12/RV12/rtl/verilog/ahb3lite/biu_ahb3lite.sv:110]
ERROR: [Synth 8-36] 'HBURST_SIZE' is not declared [/var/jenkins_home/workspace/RV12/RV12/rtl/verilog/ahb3lite/biu_ahb3lite.sv:135]
ERROR: [Synth 8-9960] range must be bounded by constant expressions [/var/jenkins_home/workspace/RV12/RV12/rtl/verilog/ahb3lite/biu_ahb3lite.sv:135]
ERROR: [Synth 8-36] 'HBURST_SINGLE' is not declared [/var/jenkins_home/workspace/RV12/RV12/rtl/verilog/ahb3lite/biu_ahb3lite.sv:139]
ERROR: [Synth 8-36] 'HBURST_INCR' is not declared [/var/jenkins_home/workspace/RV12/RV12/rtl/verilog/ahb3lite/biu_ahb3lite.sv:140]
ERROR: [Synth 8-439] module 'Controller' not found [/eda/processor_ci/rtl/RV12.sv:69]
ERROR: [Synth 8-6156] failed synthesizing module 'processorci_top' [/eda/processor_ci/rtl/RV12.sv:5]
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
make: *** [/eda/processor_ci/makefiles/digilent_arty_a7_100t.mk:12: digilent_arty_a7_100t.bit] Error 1

Traceback (most recent call last):
  File "/eda/processor_ci/main.py", line 142, in <module>
    main(
  File "/eda/processor_ci/main.py", line 89, in main
    build(build_file_path, board_name, toolchain_path)
  File "/eda/processor_ci/core/fpga.py", line 296, in build
    raise subprocess.CalledProcessError(process.returncode, 'make')
subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2.
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash digilent_arty_a7_100t)
Stage "Flash digilent_arty_a7_100t" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Test digilent_arty_a7_100t)
Stage "Test digilent_arty_a7_100t" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Lock released on resource [Resource: digilent_arty_a7_100t]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Failed in branch digilent_arty_a7_100t
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Declarative: Post Actions)
[Pipeline] junit
Recording test results
No test report files were found. Configuration error?
Error when executing always post condition:
Also:   org.jenkinsci.plugins.workflow.actions.ErrorAction$ErrorId: 6925e1b1-2268-4823-b949-89109f0e22d5
hudson.AbortException: No test report files were found. Configuration error?
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser$ParseResultCallable.invoke(JUnitParser.java:253)
	at hudson.FilePath.act(FilePath.java:1234)
	at hudson.FilePath.act(FilePath.java:1217)
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser.parseResult(JUnitParser.java:146)
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parse(JUnitResultArchiver.java:177)
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parseAndSummarize(JUnitResultArchiver.java:282)
	at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:62)
	at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:27)
	at PluginClassLoader for workflow-step-api//org.jenkinsci.plugins.workflow.steps.SynchronousNonBlockingStepExecution.lambda$start$0(SynchronousNonBlockingStepExecution.java:49)
	at java.base/java.util.concurrent.Executors$RunnableAdapter.call(Unknown Source)
	at java.base/java.util.concurrent.FutureTask.run(Unknown Source)
	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(Unknown Source)
	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(Unknown Source)
	at java.base/java.lang.Thread.run(Unknown Source)

[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
ERROR: script returned exit code 1
Finished: FAILURE