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Start of Pipeline - (21 sec in block)
node - (20 sec in block)
node block - (19 sec in block)
stage - (4.9 sec in block)Git Clone
stage block (Git Clone) - (4.4 sec in block)
sh - (0.49 sec in self)rm -rf RV12
sh - (3.7 sec in self)git clone --recursive https://github.com/roalogic/RV12 RV12
stage - (2.2 sec in block)Simulation
stage block (Simulation) - (1.6 sec in block)
dir - (1 sec in block)RV12
dir block - (0.7 sec in block)
sh - (0.47 sec in self)
stage - (10 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (9.5 sec in block)
getContext - (0.28 sec in self)
parallel - (8.8 sec in block)
parallel block (Branch: colorlight_i9) - (56 ms in block)
stage - (7.3 sec in block)colorlight_i9
stage block (colorlight_i9) - (6.9 sec in block)
getContext - (0.73 sec in self)
stage - (1.9 sec in block)Síntese e PnR
stage block (Síntese e PnR) - (0.71 sec in block)
getContext - (0.2 sec in self)
stage - (1.9 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (0.72 sec in block)
getContext - (0.2 sec in self)
stage - (1.2 sec in block)Teste colorlight_i9
stage block (Teste colorlight_i9) - (0.61 sec in block)
getContext - (0.17 sec in self)
parallel block (Branch: digilent_nexys4_ddr) - (8.2 sec in block)
stage - (7.3 sec in block)digilent_nexys4_ddr
stage block (digilent_nexys4_ddr) - (6.7 sec in block)
getContext - (0.65 sec in self)
stage - (2 sec in block)Síntese e PnR
stage block (Síntese e PnR) - (0.92 sec in block)
getContext - (0.25 sec in self)
stage - (1.8 sec in block)Flash digilent_nexys4_ddr
stage block (Flash digilent_nexys4_ddr) - (0.8 sec in block)
getContext - (0.16 sec in self)
stage - (1.3 sec in block)Teste digilent_nexys4_ddr
stage block (Teste digilent_nexys4_ddr) - (0.72 sec in block)
getContext - (0.16 sec in self)
stage - (1.6 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (1.4 sec in block)
dir - (0.94 sec in block)RV12
dir block - (0.66 sec in block)
sh - (0.43 sec in self)rm -rf *