Console Output

Started by timer
[Pipeline] Start of Pipeline
[Pipeline] node
Running on Jenkins in /var/lib/jenkins/workspace/RV12
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone)
[Pipeline] sh
+ rm -rf RV12
[Pipeline] sh
+ git clone --recursive https://github.com/roalogic/RV12 RV12
Cloning into 'RV12'...
Submodule 'submodules/ahb3lite_pkg' (https://github.com/RoaLogic/ahb3lite_pkg.git) registered for path 'submodules/ahb3lite_pkg'
Submodule 'submodules/memory' (https://github.com/RoaLogic/memory.git) registered for path 'submodules/memory'
Cloning into '/var/lib/jenkins/workspace/RV12/RV12/submodules/ahb3lite_pkg'...
Cloning into '/var/lib/jenkins/workspace/RV12/RV12/submodules/memory'...
Submodule path 'submodules/ahb3lite_pkg': checked out '75e75f521f8c34afdc1db1ea9d5be64bffbfe11c'
Submodule path 'submodules/memory': checked out '4c4de0068f8f09189812ce510e986b86e11b99fa'
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Simulation)
[Pipeline] dir
Running in /var/lib/jenkins/workspace/RV12/RV12
[Pipeline] {
[Pipeline] sh
+ iverilog -o simulation.out -g2012 -s riscv_core rtl/verilog/ahb3lite/biu_ahb3lite.sv rtl/verilog/ahb3lite/riscv_top_ahb3lite.sv rtl/verilog/core/riscv_bp.sv rtl/verilog/core/riscv_core.sv rtl/verilog/core/riscv_du.sv rtl/verilog/core/riscv_dwb.sv rtl/verilog/core/riscv_ex.sv rtl/verilog/core/riscv_id.sv rtl/verilog/core/riscv_if.sv rtl/verilog/core/riscv_mem.sv rtl/verilog/core/riscv_parcel_queue.sv rtl/verilog/core/riscv_pd.sv rtl/verilog/core/riscv_rf.sv rtl/verilog/core/riscv_rsb.sv rtl/verilog/core/riscv_state1.10.sv rtl/verilog/core/riscv_state1.7.sv rtl/verilog/core/riscv_state1.9.sv rtl/verilog/core/riscv_state_20240411.sv rtl/verilog/core/riscv_wb.sv rtl/verilog/core/cache/riscv_cache_biu_ctrl.sv rtl/verilog/core/cache/riscv_cache_memory.sv rtl/verilog/core/cache/riscv_cache_setup.sv rtl/verilog/core/cache/riscv_cache_tag.sv rtl/verilog/core/cache/riscv_dcache_core.sv rtl/verilog/core/cache/riscv_dcache_fsm.sv rtl/verilog/core/cache/riscv_icache_core.sv rtl/verilog/core/cache/riscv_icache_fsm.sv rtl/verilog/core/cache/riscv_nodcache_core.sv rtl/verilog/core/cache/riscv_noicache_core.sv rtl/verilog/core/ex/riscv_alu.sv rtl/verilog/core/ex/riscv_bu.sv rtl/verilog/core/ex/riscv_div.sv rtl/verilog/core/ex/riscv_lsu.sv rtl/verilog/core/ex/riscv_mul.sv rtl/verilog/core/memory/riscv_dmem_ctrl.sv rtl/verilog/core/memory/riscv_imem_ctrl.sv rtl/verilog/core/memory/riscv_membuf.sv rtl/verilog/core/memory/riscv_memmisaligned.sv rtl/verilog/core/memory/riscv_mmu.sv rtl/verilog/core/memory/riscv_pmachk.sv rtl/verilog/core/memory/riscv_pmpchk.sv rtl/verilog/core/memory/riscv_wbuf.sv rtl/verilog/core/mmu/riscv_nommu.sv rtl/verilog/pkg/biu_constants_pkg.sv rtl/verilog/pkg/riscv_cache_pkg.sv rtl/verilog/pkg/riscv_du_pkg.sv rtl/verilog/pkg/riscv_opcodes_pkg.sv rtl/verilog/pkg/riscv_pma_pkg.sv rtl/verilog/pkg/riscv_rv12_pkg.sv rtl/verilog/pkg/riscv_state1.10_pkg.sv rtl/verilog/pkg/riscv_state1.7_pkg.sv rtl/verilog/pkg/riscv_state1.9_pkg.sv rtl/verilog/pkg/riscv_state_20240411_pkg.sv
rtl/verilog/ahb3lite/biu_ahb3lite.sv:48: syntax error
I give up.
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Build Pipeline)
Stage "FPGA Build Pipeline" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] parallel
[Pipeline] { (Branch: colorlight_i9)
[Pipeline] { (Branch: digilent_nexys4_ddr)
[Pipeline] stage
[Pipeline] { (colorlight_i9)
[Pipeline] stage
[Pipeline] { (digilent_nexys4_ddr)
Stage "colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
Stage "digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] stage
[Pipeline] { (Síntese e PnR)
[Pipeline] stage
[Pipeline] { (Síntese e PnR)
Stage "colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
Stage "digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash colorlight_i9)
[Pipeline] stage
[Pipeline] { (Flash digilent_nexys4_ddr)
Stage "colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
Stage "digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Teste colorlight_i9)
[Pipeline] stage
[Pipeline] { (Teste digilent_nexys4_ddr)
Stage "colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
Stage "digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] }
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] }
Failed in branch colorlight_i9
[Pipeline] }
Failed in branch digilent_nexys4_ddr
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Declarative: Post Actions)
[Pipeline] dir
Running in /var/lib/jenkins/workspace/RV12/RV12
[Pipeline] {
[Pipeline] sh
+ rm -rf DATASHEET.md LICENSE.md README.md _config.yml _layouts assets bench docs rtl sim submodules
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
ERROR: script returned exit code 2
Finished: FAILURE