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Start of Pipeline - (59 sec in block)
node - (59 sec in block)
node block - (58 sec in block)
stage - (2 sec in block)Git Clone
stage block (Git Clone) - (1.6 sec in block)
sh - (0.47 sec in self)rm -rf RPU
sh - (0.92 sec in self)git clone --recursive --depth=1 https://github.com/Domipheus/RPU RPU
stage - (5.7 sec in block)Simulation
stage block (Simulation) - (5.3 sec in block)
dir - (4.9 sec in block)RPU
dir block - (4.6 sec in block)
sh - (4.4 sec in self)/eda/oss-cad-suite/bin/ghdl -a --std=08 vhdl/constants.vhd vhdl/alu_int32_div.vhd vhdl/control_unit.vhd vhdl/core.vhd vhdl/csr_unit.vhd vhdl/lint_unit.vhd vhdl/mem_controller.vhd vhdl/pc_unit.vhd vhdl/register_set.vhd vhdl/unit_alu_RV32_I.vhd vhdl/unit_decoder_RV32I.vhd
stage - (1.7 sec in block)Utilities
stage block (Utilities) - (1.2 sec in block)
dir - (0.86 sec in block)RPU
dir block - (0.61 sec in block)
sh - (0.4 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config.json -o /jenkins/processor_ci_utils/labels
stage - (47 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (47 sec in block)
parallel - (46 sec in block)
parallel block (Branch: colorlight_i9) - (59 ms in block)
stage - (7.1 sec in block)colorlight_i9
stage block (colorlight_i9) - (6.7 sec in block)
lock - (6 sec in block)colorlight_i9
lock block - (5.3 sec in block)
stage - (2.8 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (2.2 sec in block)
dir - (1.5 sec in block)RPU
dir block - (1.1 sec in block)
echo - (0.17 sec in self)Starting synthesis for FPGA colorlight_i9.
sh - (0.66 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p RPU -b colorlight_i9
stage - (1 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (0.4 sec in block)
getContext - (0.15 sec in self)
stage - (0.67 sec in block)Test colorlight_i9
stage block (Test colorlight_i9) - (0.37 sec in block)
getContext - (0.17 sec in self)
parallel block (Branch: digilent_arty_a7_100t) - (46 sec in block)
stage - (45 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (45 sec in block)
lock - (44 sec in block)digilent_arty_a7_100t
lock block - (43 sec in block)
stage - (41 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (40 sec in block)
dir - (40 sec in block)RPU
dir block - (39 sec in block)
echo - (0.15 sec in self)Starting synthesis for FPGA digilent_arty_a7_100t.
sh - (39 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p RPU -b digilent_arty_a7_100t
stage - (0.94 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (0.36 sec in block)
getContext - (0.15 sec in self)
stage - (0.69 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (0.37 sec in block)
getContext - (0.15 sec in self)
stage - (0.77 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.53 sec in block)
junit - (0.28 sec in self)**/test-reports/*.xml