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Start of Pipeline - (5 min 32 sec in block)
node - (5 min 31 sec in block)
node block - (5 min 31 sec in block)
stage - (2 sec in block)Git Clone
stage block (Git Clone) - (1.6 sec in block)
sh - (0.46 sec in self)rm -rf RPU
sh - (0.91 sec in self)git clone --recursive --depth=1 https://github.com/Domipheus/RPU RPU
stage - (5.7 sec in block)Simulation
stage block (Simulation) - (5.2 sec in block)
dir - (4.9 sec in block)RPU
dir block - (4.6 sec in block)
sh - (4.4 sec in self)/eda/oss-cad-suite/bin/ghdl -a --std=08 vhdl/constants.vhd vhdl/alu_int32_div.vhd vhdl/control_unit.vhd vhdl/core.vhd vhdl/csr_unit.vhd vhdl/lint_unit.vhd vhdl/mem_controller.vhd vhdl/pc_unit.vhd vhdl/register_set.vhd vhdl/unit_alu_RV32_I.vhd vhdl/unit_decoder_RV32I.vhd
stage - (2.1 sec in block)Utilities
stage block (Utilities) - (1.6 sec in block)
dir - (1.2 sec in block)RPU
dir block - (1 sec in block)
sh - (0.83 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config.json -o /jenkins/processor_ci_utils/labels
stage - (5 min 20 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (5 min 19 sec in block)
parallel - (5 min 19 sec in block)
parallel block (Branch: colorlight_i9) - (51 ms in block)
stage - (7 sec in block)colorlight_i9
stage block (colorlight_i9) - (6.7 sec in block)
lock - (5.9 sec in block)colorlight_i9
lock block - (5.3 sec in block)
stage - (2.8 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (2.2 sec in block)
dir - (1.5 sec in block)RPU
dir block - (1.2 sec in block)
echo - (0.17 sec in self)Starting synthesis for FPGA colorlight_i9.
sh - (0.64 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p RPU -b colorlight_i9
stage - (0.96 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (0.38 sec in block)
getContext - (0.17 sec in self)
stage - (0.68 sec in block)Test colorlight_i9
stage block (Test colorlight_i9) - (0.38 sec in block)
getContext - (0.15 sec in self)
parallel block (Branch: digilent_arty_a7_100t) - (5 min 18 sec in block)
stage - (5 min 18 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (5 min 17 sec in block)
lock - (5 min 17 sec in block)digilent_arty_a7_100t
lock block - (5 min 16 sec in block)
stage - (5 min 8 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (5 min 8 sec in block)
dir - (5 min 7 sec in block)RPU
dir block - (5 min 7 sec in block)
echo - (0.15 sec in self)Starting synthesis for FPGA digilent_arty_a7_100t.
sh - (5 min 6 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p RPU -b digilent_arty_a7_100t
stage - (5.1 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (4.6 sec in block)
dir - (4.2 sec in block)RPU
dir block - (4 sec in block)
echo - (0.17 sec in self)Flashing FPGA digilent_arty_a7_100t.
sh - (3.6 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p RPU -b digilent_arty_a7_100t -l
stage - (2.1 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (1.8 sec in block)
echo - (0.21 sec in self)Testing FPGA digilent_arty_a7_100t.
dir - (1.3 sec in block)RPU
dir block - (1 sec in block)
sh - (0.46 sec in self)echo "Test for FPGA in /dev/ttyUSB1"
sh - (0.39 sec in self)python3 /eda/processor_ci_tests/test_runner/run.py --config /eda/processor_ci_tests/test_runner/config.json --port /dev/ttyUSB1
stage - (0.78 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.55 sec in block)
junit - (0.27 sec in self)**/test-reports/*.xml