Console Output

+ python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p RPU -b digilent_nexys4_ddr -l
Arquivo de configura����o final gerado em /var/lib/jenkins/workspace/RPU/RPU/build_digilent_nexys4_ddr.tcl
Makefile executado com sucesso.
Sa��da do Makefile:
Flashing the FPGA...
/eda/oss-cad-suite/bin/openFPGALoader -b nexys_a7_100 digilent_nexys4_ddr.bit
empty
Jtag frequency : requested 6.00MHz   -> real 6.00MHz  
Open file DONE
Parse file DONE
load program

Load SRAM: [=========                                         ] 18.00%
Load SRAM: [===================                               ] 38.00%
Load SRAM: [=============================                     ] 57.00%
Load SRAM: [=======================================           ] 77.00%
Load SRAM: [================================================= ] 97.00%
Load SRAM: [===================================================] 100.00%
Done
Shift IR 35
ir: 1 isc_done 1 isc_ena 0 init 1 done 1