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Start of Pipeline - (11 min in block)
node - (11 min in block)
node block - (4 min 58 sec in block)
stage - (2.4 sec in block)Git Clone
stage block (Git Clone) - (1.9 sec in block)
sh - (0.64 sec in self)rm -rf RPU
sh - (0.94 sec in self)git clone --recursive https://github.com/Domipheus/RPU RPU
stage - (1.6 sec in block)Simulation
stage block (Simulation) - (1.1 sec in block)
dir - (0.84 sec in block)RPU
dir block - (0.6 sec in block)
sh - (0.4 sec in self)ghdl -a --std=08 vhdl/constants.vhd vhdl/alu_int32_div.vhd vhdl/control_unit.vhd vhdl/core.vhd vhdl/csr_unit.vhd vhdl/lint_unit.vhd vhdl/mem_controller.vhd vhdl/pc_unit.vhd vhdl/register_set.vhd vhdl/unit_alu_RV32_I.vhd vhdl/unit_decoder_RV32I.vhd
stage - (4 min 50 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (4 min 49 sec in block)
parallel - (4 min 48 sec in block)
parallel block (Branch: colorlight_i9) - (56 ms in block)
stage - (6.8 sec in block)colorlight_i9
stage block (colorlight_i9) - (6.5 sec in block)
lock - (5.7 sec in block)colorlight_i9
lock block - (4.9 sec in block)
stage - (2.4 sec in block)Síntese e PnR
stage block (Síntese e PnR) - (1.7 sec in block)
dir - (1.2 sec in block)RPU
dir block - (0.88 sec in block)
echo - (0.2 sec in self)Iniciando síntese para FPGA colorlight_i9.
sh - (0.49 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p RPU -b colorlight_i9
stage - (1 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (0.39 sec in block)
getContext - (0.2 sec in self)
stage - (0.76 sec in block)Teste colorlight_i9
stage block (Teste colorlight_i9) - (0.44 sec in block)
getContext - (0.2 sec in self)
parallel block (Branch: digilent_nexys4_ddr) - (4 min 48 sec in block)
stage - (4 min 47 sec in block)digilent_nexys4_ddr
stage block (digilent_nexys4_ddr) - (4 min 47 sec in block)
lock - (4 min 46 sec in block)digilent_nexys4_ddr
lock block - (8.1 sec in block)
stage - (3.9 sec in block)Síntese e PnR
stage block (Síntese e PnR) - (2.8 sec in block)
dir - (1.9 sec in block)RPU
dir block - (1.3 sec in block)
echo - (0.32 sec in self)Iniciando síntese para FPGA digilent_nexys4_ddr.
sh - (0.64 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p RPU -b digilent_nexys4_ddr
stage - (1.9 sec in block)Flash digilent_nexys4_ddr
stage block (Flash digilent_nexys4_ddr) - (0.65 sec in block)
getContext - (0.32 sec in self)
stage - (1.3 sec in block)Teste digilent_nexys4_ddr
stage block (Teste digilent_nexys4_ddr) - (0.76 sec in block)
getContext - (0.34 sec in self)
stage - (2.9 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (2.4 sec in block)
dir - (1.5 sec in block)RPU
dir block - (1 sec in block)
sh - (0.51 sec in self)rm -rf *