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Start of Pipeline - (9 min 0 sec in block)
node - (8 min 59 sec in block)
node block - (6 min 30 sec in block)
stage - (2.5 sec in block)Git Clone
stage block (Git Clone) - (1.9 sec in block)
sh - (0.64 sec in self)rm -rf RISC-V
sh - (0.97 sec in self)git clone --recursive --depth=1 https://github.com/yavuz650/RISC-V RISC-V
stage - (1.7 sec in block)Simulation
stage block (Simulation) - (1.2 sec in block)
dir - (0.91 sec in block)RISC-V
dir block - (0.65 sec in block)
sh - (0.41 sec in self)/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s core core/ALU.v core/control_unit.v core/core.v core/core_wb.v core/csr_unit.v core/forwarding_unit.v core/hazard_detection_unit.v core/imm_decoder.v core/load_store_unit.v core/muldiv/MULDIV_ctrl.v core/muldiv/MULDIV_in.v core/muldiv/MULDIV_top.v core/muldiv/MUL_DIV_out.v core/muldiv/divider_32.v core/muldiv/multiplier_32.v
stage - (1.6 sec in block)Utilities
stage block (Utilities) - (1.2 sec in block)
dir - (0.85 sec in block)RISC-V
dir block - (0.6 sec in block)
sh - (0.41 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config.json -o /jenkins/processor_ci_utils/labels
stage - (6 min 22 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (6 min 22 sec in block)
parallel - (6 min 21 sec in block)
parallel block (Branch: colorlight_i9) - (51 ms in block)
stage - (6.2 sec in block)colorlight_i9
stage block (colorlight_i9) - (5.9 sec in block)
lock - (5.1 sec in block)colorlight_i9
lock block - (4.5 sec in block)
stage - (2.1 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (1.5 sec in block)
dir - (1 sec in block)RISC-V
dir block - (0.75 sec in block)
echo - (0.15 sec in self)Starting synthesis for FPGA colorlight_i9.
sh - (0.46 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p RISC-V -b colorlight_i9
stage - (0.92 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (0.34 sec in block)
getContext - (0.15 sec in self)
stage - (0.68 sec in block)Test colorlight_i9
stage block (Test colorlight_i9) - (0.36 sec in block)
getContext - (0.16 sec in self)
parallel block (Branch: digilent_arty_a7_100t) - (6 min 20 sec in block)
stage - (6 min 20 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (6 min 19 sec in block)
lock - (6 min 18 sec in block)digilent_arty_a7_100t
lock block - (5 min 16 sec in block)
stage - (5 min 8 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (5 min 8 sec in block)
dir - (5 min 7 sec in block)RISC-V
dir block - (5 min 7 sec in block)
echo - (0.31 sec in self)Starting synthesis for FPGA digilent_arty_a7_100t.
sh - (5 min 6 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p RISC-V -b digilent_arty_a7_100t
stage - (5.1 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (4.6 sec in block)
dir - (4.2 sec in block)RISC-V
dir block - (4 sec in block)
echo - (0.16 sec in self)Flashing FPGA digilent_arty_a7_100t.
sh - (3.6 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p RISC-V -b digilent_arty_a7_100t -l
stage - (2.1 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (1.9 sec in block)
echo - (0.22 sec in self)Testing FPGA digilent_arty_a7_100t.
dir - (1.3 sec in block)RISC-V
dir block - (1 sec in block)
sh - (0.46 sec in self)echo "Test for FPGA in /dev/ttyUSB1"
sh - (0.42 sec in self)python3 /eda/processor_ci_tests/test_runner/run.py --config /eda/processor_ci_tests/test_runner/config.json --port /dev/ttyUSB1
stage - (0.76 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.51 sec in block)
junit - (0.26 sec in self)**/test-reports/*.xml