Console Output
+ /eda/oss-cad-suite/bin/nextpnr-ecp5 --json ./build/out.json --write ./build/out_pnr.json --45k --lpf Pequeno-Risco-5/fpga/ecp5/pinout.lpf --textcfg ./build/out.config --package CABGA381 --speed 6 --ignore-loops --lpf-allow-unconstrained
Info: constraining clock net 'clk' to 25.00 MHz
Info: Logic utilisation before packing:
Info: Total LUT4s: 13/43848 0%
Info: logic LUTs: 11/43848 0%
Info: carry LUTs: 2/43848 0%
Info: RAM LUTs: 0/ 5481 0%
Info: RAMW LUTs: 0/10962 0%
Info: Total DFFs: 10/43848 0%
Info: Packing IOs..
Info: pin 'tx$tr_io' constrained to Bel 'X90/Y20/PIOA'.
Info: pin 'rx$tr_io' constrained to Bel 'X90/Y20/PIOC'.
Info: pin 'reset$tr_io' constrained to Bel 'X0/Y29/PIOA'.
Info: pin 'led[7]$tr_io' constrained to Bel 'X90/Y20/PIOD'.
Info: pin 'led[6]$tr_io' constrained to Bel 'X0/Y44/PIOD'.
Info: pin 'led[5]$tr_io' constrained to Bel 'X0/Y59/PIOA'.
Info: pin 'led[4]$tr_io' constrained to Bel 'X15/Y71/PIOB'.
Info: pin 'led[3]$tr_io' constrained to Bel 'X90/Y29/PIOC'.
Info: pin 'led[2]$tr_io' constrained to Bel 'X90/Y44/PIOB'.
Info: pin 'led[1]$tr_io' constrained to Bel 'X0/Y44/PIOC'.
Info: pin 'led[0]$tr_io' constrained to Bel 'X0/Y59/PIOC'.
Info: pin 'clk$tr_io' constrained to Bel 'X0/Y68/PIOC'.
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 4 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info: promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0x3f422eed
Info: Device utilisation:
Info: TRELLIS_IO: 12/ 245 4%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 0/ 72 0%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 0/ 4 0%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 10/43848 0%
Info: TRELLIS_COMB: 19/43848 0%
Info: TRELLIS_RAMW: 0/ 5481 0%
Info: Placed 12 cells based on constraints.
Info: Creating initial analytic placement for 19 cells, random placement wirelen = 1474.
Info: at initial placer iter 0, wirelen = 557
Info: at initial placer iter 1, wirelen = 540
Info: at initial placer iter 2, wirelen = 529
Info: at initial placer iter 3, wirelen = 530
Info: Running main analytical placer, max placement attempts per cell = 10000.
Info: at iteration #1, type ALL: wirelen solved = 524, spread = 535, legal = 538; time = 0.01s
Info: HeAP Placer Time: 0.05s
Info: of which solving equations: 0.00s
Info: of which spreading cells: 0.00s
Info: of which strict legalisation: 0.00s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 20, wirelen = 538
Info: at iteration #4: temp = 0.000000, timing cost = 23, wirelen = 503
Info: SA placement time 0.00s
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 107.75 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 11.10 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 15.52 ns
Info: Slack histogram:
Info: legend: * represents 1 endpoint(s)
Info: + represents [1,1) endpoint(s)
Info: [ 30719, 31146) |**
Info: [ 31146, 31573) |
Info: [ 31573, 32000) |**
Info: [ 32000, 32427) |
Info: [ 32427, 32854) |
Info: [ 32854, 33281) |
Info: [ 33281, 33708) |
Info: [ 33708, 34135) |
Info: [ 34135, 34562) |*
Info: [ 34562, 34989) |
Info: [ 34989, 35416) |
Info: [ 35416, 35843) |*
Info: [ 35843, 36270) |
Info: [ 36270, 36697) |*
Info: [ 36697, 37124) |
Info: [ 37124, 37551) |
Info: [ 37551, 37978) |***
Info: [ 37978, 38405) |***
Info: [ 38405, 38832) |**
Info: [ 38832, 39259) |***
Info: Checksum: 0xc37b1598
Info: Routing globals...
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 56 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 56 | 0 53 | 0 53 | 0| 0.02 0.02|
Info: Routing complete.
Info: Router1 time 0.02s
Info: Checksum: 0xdff3c86b
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: curr total
Info: 0.5 0.5 Source Core.Immediate_generator.instruction_TRELLIS_FF_Q.Q
Info: 0.8 1.3 Net Core.instruction[10] (4,45) -> (4,44)
Info: Sink Core.Alu.ALU_Result_LUT4_Z_1.C
Info: Defined in:
Info: Pequeno-Risco-5/fpga/ecp5/main.v:11.3-15.2
Info: Pequeno-Risco-5/src/registers.v:7.22-7.35
Info: Pequeno-Risco-5/src/core.v:103.11-114.2
Info: 0.2 1.5 Source Core.Alu.ALU_Result_LUT4_Z_1.F
Info: 3.5 5.0 Net Core.data_address[1] (4,44) -> (60,45)
Info: Sink Core.registers.register15_TRELLIS_FF_Q.M
Info: Defined in:
Info: Pequeno-Risco-5/fpga/ecp5/main.v:11.3-15.2
Info: Pequeno-Risco-5/src/registers.v:8.23-8.32
Info: Pequeno-Risco-5/src/core.v:103.11-114.2
Info: 0.0 5.0 Setup Core.registers.register15_TRELLIS_FF_Q.M
Info: 0.8 ns logic, 4.3 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: curr total
Info: 0.0 0.0 Source reset$tr_io.O
Info: 4.5 4.5 Net reset$TRELLIS_IO_IN (0,29) -> (60,45)
Info: Sink Core.registers.register15_TRELLIS_FF_Q_5.LSR
Info: Defined in:
Info: Pequeno-Risco-5/fpga/ecp5/main.v:3.16-3.21
Info: 0.4 4.9 Setup Core.registers.register15_TRELLIS_FF_Q_5.LSR
Info: 0.4 ns logic, 4.5 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: curr total
Info: 0.5 0.5 Source Core.registers.register15_TRELLIS_FF_Q_4.Q
Info: 2.2 2.7 Net Core.registers.register15[3] (5,43) -> (16,32)
Info: Sink led_LUT4_Z.D
Info: Defined in:
Info: Pequeno-Risco-5/fpga/ecp5/main.v:11.3-15.2
Info: Pequeno-Risco-5/src/registers.v:29.12-29.22
Info: Pequeno-Risco-5/src/core.v:103.11-114.2
Info: 0.2 2.9 Source led_LUT4_Z.F
Info: 4.4 7.3 Net led[3]$TRELLIS_IO_OUT (16,32) -> (90,29)
Info: Sink led[3]$tr_io.I
Info: Defined in:
Info: Pequeno-Risco-5/fpga/ecp5/main.v:6.22-6.25
Info: 0.8 ns logic, 6.6 ns routing
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 198.89 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 4.93 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 7.34 ns
Info: Slack histogram:
Info: legend: * represents 1 endpoint(s)
Info: + represents [1,1) endpoint(s)
Info: [ 34972, 35168) |**
Info: [ 35168, 35364) |
Info: [ 35364, 35560) |
Info: [ 35560, 35756) |
Info: [ 35756, 35952) |
Info: [ 35952, 36148) |
Info: [ 36148, 36344) |
Info: [ 36344, 36540) |**
Info: [ 36540, 36736) |*
Info: [ 36736, 36932) |
Info: [ 36932, 37128) |
Info: [ 37128, 37324) |**
Info: [ 37324, 37520) |
Info: [ 37520, 37716) |*
Info: [ 37716, 37912) |*
Info: [ 37912, 38108) |*
Info: [ 38108, 38304) |**
Info: [ 38304, 38500) |*
Info: [ 38500, 38696) |
Info: [ 38696, 38892) |*****
Info: Program finished normally.
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