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Start of Pipeline - (5 min 20 sec in block)
node - (5 min 20 sec in block)
node block - (5 min 19 sec in block)
stage - (2.1 sec in block)Git Clone
stage block (Git Clone) - (1.6 sec in block)
sh - (0.45 sec in self)rm -rf Pequeno-Risco-5
sh - (0.93 sec in self)git clone --recursive https://github.com/JN513/Pequeno-Risco-5 Pequeno-Risco-5
stage - (1.8 sec in block)Simulation
stage block (Simulation) - (1.3 sec in block)
dir - (0.9 sec in block)Pequeno-Risco-5
dir block - (0.63 sec in block)
sh - (0.43 sec in self)iverilog -o simulation.out -g2005 -s Core src/alu.v src/alu_control.v src/control_unit.v src/core.v src/immediate_generator.v src/mux.v src/pc.v src/registers.v src/instruction_memory.v src/data_memory.v
stage - (5 min 14 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (5 min 13 sec in block)
parallel - (5 min 13 sec in block)
parallel block (Branch: colorlight_i9) - (56 ms in block)
stage - (4 min 35 sec in block)colorlight_i9
stage block (colorlight_i9) - (4 min 35 sec in block)
lock - (4 min 34 sec in block)colorlight_i9
lock block - (4 min 33 sec in block)
stage - (4 min 8 sec in block)Síntese e PnR
stage block (Síntese e PnR) - (4 min 8 sec in block)
dir - (4 min 7 sec in block)Pequeno-Risco-5
dir block - (4 min 7 sec in block)
echo - (0.17 sec in self)Iniciando síntese para FPGA colorlight_i9.
sh - (4 min 6 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Pequeno-Risco-5 -b colorlight_i9
stage - (16 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (16 sec in block)
dir - (15 sec in block)Pequeno-Risco-5
dir block - (15 sec in block)
echo - (0.18 sec in self)FPGA colorlight_i9 bloqueada para flash.
sh - (15 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Pequeno-Risco-5 -b colorlight_i9 -l
stage - (6.4 sec in block)Teste colorlight_i9
stage block (Teste colorlight_i9) - (6.1 sec in block)
echo - (0.22 sec in self)Testando FPGA colorlight_i9.
dir - (5.5 sec in block)Pequeno-Risco-5
dir block - (5.2 sec in block)
sh - (5 sec in self)PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyACM0 python /eda/processor-ci-communication/run_tests.py
parallel block (Branch: digilent_nexys4_ddr) - (5 min 12 sec in block)
stage - (5 min 12 sec in block)digilent_nexys4_ddr
stage block (digilent_nexys4_ddr) - (5 min 12 sec in block)
lock - (5 min 11 sec in block)digilent_nexys4_ddr
lock block - (5 min 10 sec in block)
stage - (4 min 53 sec in block)Síntese e PnR
stage block (Síntese e PnR) - (4 min 53 sec in block)
dir - (4 min 52 sec in block)Pequeno-Risco-5
dir block - (4 min 52 sec in block)
echo - (0.2 sec in self)Iniciando síntese para FPGA digilent_nexys4_ddr.
sh - (4 min 51 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Pequeno-Risco-5 -b digilent_nexys4_ddr
stage - (14 sec in block)Flash digilent_nexys4_ddr
stage block (Flash digilent_nexys4_ddr) - (13 sec in block)
dir - (13 sec in block)Pequeno-Risco-5
dir block - (12 sec in block)
echo - (0.17 sec in self)FPGA digilent_nexys4_ddr bloqueada para flash.
sh - (12 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Pequeno-Risco-5 -b digilent_nexys4_ddr -l
stage - (1.5 sec in block)Teste digilent_nexys4_ddr
stage block (Teste digilent_nexys4_ddr) - (1.1 sec in block)
echo - (0.24 sec in self)Testando FPGA digilent_nexys4_ddr.
dir - (0.47 sec in block)Pequeno-Risco-5
dir block - (0.19 sec in block)
stage - (1 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.86 sec in block)
junit - (0.59 sec in self)**/test-reports/*.xml