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Start of Pipeline - (12 min in block)
node - (12 min in block)
node block - (39 sec in block)
stage - (4 sec in block)Git Clone
stage block (Git Clone) - (2.6 sec in block)
sh - (0.74 sec in self)rm -rf Pequeno-Risco-5
sh - (1.4 sec in self)git clone --recursive https://github.com/JN513/Pequeno-Risco-5 Pequeno-Risco-5
stage - (3.3 sec in block)Simulation
stage block (Simulation) - (2.3 sec in block)
dir - (1.5 sec in block)Pequeno-Risco-5
dir block - (1 sec in block)
sh - (0.58 sec in self)iverilog -o simulation.out -g2005 -s Core src/alu.v src/alu_control.v src/control_unit.v src/core.v src/immediate_generator.v src/mux.v src/pc.v src/registers.v src/instruction_memory.v src/data_memory.v
stage - (28 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (26 sec in block)
parallel - (25 sec in block)
parallel block (Branch: colorlight_i9) - (0.13 sec in block)
stage - (15 sec in block)colorlight_i9
stage block (colorlight_i9) - (14 sec in block)
lock - (12 sec in block)colorlight_i9
lock block - (8.8 sec in block)
stage - (4.9 sec in block)Síntese e PnR
stage block (Síntese e PnR) - (3.8 sec in block)
dir - (2.8 sec in block)Pequeno-Risco-5
dir block - (2.3 sec in block)
echo - (0.33 sec in self)Iniciando síntese para FPGA colorlight_i9.
sh - (1.2 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Pequeno-Risco-5 -b colorlight_i9
stage - (1.8 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (0.77 sec in block)
getContext - (0.37 sec in self)
stage - (1.2 sec in block)Teste colorlight_i9
stage block (Teste colorlight_i9) - (0.7 sec in block)
getContext - (0.33 sec in self)
parallel block (Branch: digilent_nexys4_ddr) - (24 sec in block)
stage - (22 sec in block)digilent_nexys4_ddr
stage block (digilent_nexys4_ddr) - (22 sec in block)
lock - (20 sec in block)digilent_nexys4_ddr
lock block - (17 sec in block)
stage - (11 sec in block)Síntese e PnR
stage block (Síntese e PnR) - (10 sec in block)
dir - (4.1 sec in block)Pequeno-Risco-5
dir block - (2.6 sec in block)
echo - (0.38 sec in self)Iniciando síntese para FPGA digilent_nexys4_ddr.
sh - (1.8 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Pequeno-Risco-5 -b digilent_nexys4_ddr
stage - (2 sec in block)Flash digilent_nexys4_ddr
stage block (Flash digilent_nexys4_ddr) - (0.81 sec in block)
getContext - (0.35 sec in self)
stage - (1.6 sec in block)Teste digilent_nexys4_ddr
stage block (Teste digilent_nexys4_ddr) - (0.99 sec in block)
getContext - (0.54 sec in self)
stage - (2.9 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (2.4 sec in block)
dir - (1.4 sec in block)Pequeno-Risco-5
dir block - (0.97 sec in block)
sh - (0.51 sec in self)rm -rf *