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Analyzing top.Core.Data_memory.ram write port 446.
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Analyzing top.Core.Data_memory.ram write port 906.
Analyzing top.Core.Data_memory.ram write port 907.
Analyzing top.Core.Data_memory.ram write port 908.
Analyzing top.Core.Data_memory.ram write port 909.
Analyzing top.Core.Data_memory.ram write port 910.
Analyzing top.Core.Data_memory.ram write port 911.
Analyzing top.Core.Data_memory.ram write port 912.
Analyzing top.Core.Data_memory.ram write port 913.
Analyzing top.Core.Data_memory.ram write port 914.
Analyzing top.Core.Data_memory.ram write port 915.
Analyzing top.Core.Data_memory.ram write port 916.
Analyzing top.Core.Data_memory.ram write port 917.
Analyzing top.Core.Data_memory.ram write port 918.
Analyzing top.Core.Data_memory.ram write port 919.
Analyzing top.Core.Data_memory.ram write port 920.
Analyzing top.Core.Data_memory.ram write port 921.
Analyzing top.Core.Data_memory.ram write port 922.
Analyzing top.Core.Data_memory.ram write port 923.
Analyzing top.Core.Data_memory.ram write port 924.
Analyzing top.Core.Data_memory.ram write port 925.
Analyzing top.Core.Data_memory.ram write port 926.
Analyzing top.Core.Data_memory.ram write port 927.
Analyzing top.Core.Data_memory.ram write port 928.
Analyzing top.Core.Data_memory.ram write port 929.
Analyzing top.Core.Data_memory.ram write port 930.
Analyzing top.Core.Data_memory.ram write port 931.
Analyzing top.Core.Data_memory.ram write port 932.
Analyzing top.Core.Data_memory.ram write port 933.
Analyzing top.Core.Data_memory.ram write port 934.
Analyzing top.Core.Data_memory.ram write port 935.
Analyzing top.Core.Data_memory.ram write port 936.
Analyzing top.Core.Data_memory.ram write port 937.
Analyzing top.Core.Data_memory.ram write port 938.
Analyzing top.Core.Data_memory.ram write port 939.
Analyzing top.Core.Data_memory.ram write port 940.
Analyzing top.Core.Data_memory.ram write port 941.
Analyzing top.Core.Data_memory.ram write port 942.
Analyzing top.Core.Data_memory.ram write port 943.
Analyzing top.Core.Data_memory.ram write port 944.
Analyzing top.Core.Data_memory.ram write port 945.
Analyzing top.Core.Data_memory.ram write port 946.
Analyzing top.Core.Data_memory.ram write port 947.
Analyzing top.Core.Data_memory.ram write port 948.
Analyzing top.Core.Data_memory.ram write port 949.
Analyzing top.Core.Data_memory.ram write port 950.
Analyzing top.Core.Data_memory.ram write port 951.
Analyzing top.Core.Data_memory.ram write port 952.
Analyzing top.Core.Data_memory.ram write port 953.
Analyzing top.Core.Data_memory.ram write port 954.
Analyzing top.Core.Data_memory.ram write port 955.
Analyzing top.Core.Data_memory.ram write port 956.
Analyzing top.Core.Data_memory.ram write port 957.
Analyzing top.Core.Data_memory.ram write port 958.
Analyzing top.Core.Data_memory.ram write port 959.
Analyzing top.Core.Data_memory.ram write port 960.
Analyzing top.Core.Data_memory.ram write port 961.
Analyzing top.Core.Data_memory.ram write port 962.
Analyzing top.Core.Data_memory.ram write port 963.
Analyzing top.Core.Data_memory.ram write port 964.
Analyzing top.Core.Data_memory.ram write port 965.
Analyzing top.Core.Data_memory.ram write port 966.
Analyzing top.Core.Data_memory.ram write port 967.
Analyzing top.Core.Data_memory.ram write port 968.
Analyzing top.Core.Data_memory.ram write port 969.
Analyzing top.Core.Data_memory.ram write port 970.
Analyzing top.Core.Data_memory.ram write port 971.
Analyzing top.Core.Data_memory.ram write port 972.
Analyzing top.Core.Data_memory.ram write port 973.
Analyzing top.Core.Data_memory.ram write port 974.
Analyzing top.Core.Data_memory.ram write port 975.
Analyzing top.Core.Data_memory.ram write port 976.
Analyzing top.Core.Data_memory.ram write port 977.
Analyzing top.Core.Data_memory.ram write port 978.
Analyzing top.Core.Data_memory.ram write port 979.
Analyzing top.Core.Data_memory.ram write port 980.
Analyzing top.Core.Data_memory.ram write port 981.
Analyzing top.Core.Data_memory.ram write port 982.
Analyzing top.Core.Data_memory.ram write port 983.
Analyzing top.Core.Data_memory.ram write port 984.
Analyzing top.Core.Data_memory.ram write port 985.
Analyzing top.Core.Data_memory.ram write port 986.
Analyzing top.Core.Data_memory.ram write port 987.
Analyzing top.Core.Data_memory.ram write port 988.
Analyzing top.Core.Data_memory.ram write port 989.
Analyzing top.Core.Data_memory.ram write port 990.
Analyzing top.Core.Data_memory.ram write port 991.
Analyzing top.Core.Data_memory.ram write port 992.
Analyzing top.Core.Data_memory.ram write port 993.
Analyzing top.Core.Data_memory.ram write port 994.
Analyzing top.Core.Data_memory.ram write port 995.
Analyzing top.Core.Data_memory.ram write port 996.
Analyzing top.Core.Data_memory.ram write port 997.
Analyzing top.Core.Data_memory.ram write port 998.
Analyzing top.Core.Data_memory.ram write port 999.
Analyzing top.Core.Data_memory.ram write port 1000.
Analyzing top.Core.Data_memory.ram write port 1001.
Analyzing top.Core.Data_memory.ram write port 1002.
Analyzing top.Core.Data_memory.ram write port 1003.
Analyzing top.Core.Data_memory.ram write port 1004.
Analyzing top.Core.Data_memory.ram write port 1005.
Analyzing top.Core.Data_memory.ram write port 1006.
Analyzing top.Core.Data_memory.ram write port 1007.
Analyzing top.Core.Data_memory.ram write port 1008.
Analyzing top.Core.Data_memory.ram write port 1009.
Analyzing top.Core.Data_memory.ram write port 1010.
Analyzing top.Core.Data_memory.ram write port 1011.
Analyzing top.Core.Data_memory.ram write port 1012.
Analyzing top.Core.Data_memory.ram write port 1013.
Analyzing top.Core.Data_memory.ram write port 1014.
Analyzing top.Core.Data_memory.ram write port 1015.
Analyzing top.Core.Data_memory.ram write port 1016.
Analyzing top.Core.Data_memory.ram write port 1017.
Analyzing top.Core.Data_memory.ram write port 1018.
Analyzing top.Core.Data_memory.ram write port 1019.
Analyzing top.Core.Data_memory.ram write port 1020.
Analyzing top.Core.Data_memory.ram write port 1021.
Analyzing top.Core.Data_memory.ram write port 1022.
Analyzing top.Core.Data_memory.ram write port 1023.
12.24.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).
12.24.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
Checking read port `\Core.Data_memory.ram'[0] in module `\top': no output FF found.
Checking read port `\Core.Instruction_memory.memory'[0] in module `\top': no output FF found.
Checking read port address `\Core.Data_memory.ram'[0] in module `\top': no address FF found.
Checking read port address `\Core.Instruction_memory.memory'[0] in module `\top': address FF has fully-defined init value, not supported.
12.24.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
12.24.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
Consolidating write ports of memory top.Core.Data_memory.ram by address:
Merging ports 0, 1 (address 10'0000000000).
Merging ports 0, 2 (address 10'0000000000).
Merging ports 0, 3 (address 10'0000000000).
Merging ports 0, 4 (address 10'0000000000).
Merging ports 0, 5 (address 10'0000000000).
Merging ports 0, 6 (address 10'0000000000).
Merging ports 0, 7 (address 10'0000000000).
Merging ports 0, 8 (address 10'0000000000).
Merging ports 0, 9 (address 10'0000000000).
Merging ports 0, 10 (address 10'0000000000).
Merging ports 0, 11 (address 10'0000000000).
Merging ports 0, 12 (address 10'0000000000).
Merging ports 0, 13 (address 10'0000000000).
Merging ports 0, 14 (address 10'0000000000).
Merging ports 0, 15 (address 10'0000000000).
Merging ports 0, 16 (address 10'0000000000).
Merging ports 0, 17 (address 10'0000000000).
Merging ports 0, 18 (address 10'0000000000).
Merging ports 0, 19 (address 10'0000000000).
Merging ports 0, 20 (address 10'0000000000).
Merging ports 0, 21 (address 10'0000000000).
Merging ports 0, 22 (address 10'0000000000).
Merging ports 0, 23 (address 10'0000000000).
Merging ports 0, 24 (address 10'0000000000).
Merging ports 0, 25 (address 10'0000000000).
Merging ports 0, 26 (address 10'0000000000).
Merging ports 0, 27 (address 10'0000000000).
Merging ports 0, 28 (address 10'0000000000).
Merging ports 0, 29 (address 10'0000000000).
Merging ports 0, 30 (address 10'0000000000).
Merging ports 0, 31 (address 10'0000000000).
Merging ports 0, 32 (address 10'0000000000).
Merging ports 0, 33 (address 10'0000000000).
Merging ports 0, 34 (address 10'0000000000).
Merging ports 0, 35 (address 10'0000000000).
Merging ports 0, 36 (address 10'0000000000).
Merging ports 0, 37 (address 10'0000000000).
Merging ports 0, 38 (address 10'0000000000).
Merging ports 0, 39 (address 10'0000000000).
Merging ports 0, 40 (address 10'0000000000).
Merging ports 0, 41 (address 10'0000000000).
Merging ports 0, 42 (address 10'0000000000).
Merging ports 0, 43 (address 10'0000000000).
Merging ports 0, 44 (address 10'0000000000).
Merging ports 0, 45 (address 10'0000000000).
Merging ports 0, 46 (address 10'0000000000).
Merging ports 0, 47 (address 10'0000000000).
Merging ports 0, 48 (address 10'0000000000).
Merging ports 0, 49 (address 10'0000000000).
Merging ports 0, 50 (address 10'0000000000).
Merging ports 0, 51 (address 10'0000000000).
Merging ports 0, 52 (address 10'0000000000).
Merging ports 0, 53 (address 10'0000000000).
Merging ports 0, 54 (address 10'0000000000).
Merging ports 0, 55 (address 10'0000000000).
Merging ports 0, 56 (address 10'0000000000).
Merging ports 0, 57 (address 10'0000000000).
Merging ports 0, 58 (address 10'0000000000).
Merging ports 0, 59 (address 10'0000000000).
Merging ports 0, 60 (address 10'0000000000).
Merging ports 0, 61 (address 10'0000000000).
Merging ports 0, 62 (address 10'0000000000).
Merging ports 0, 63 (address 10'0000000000).
Merging ports 0, 64 (address 10'0000000000).
Merging ports 0, 65 (address 10'0000000000).
Merging ports 0, 66 (address 10'0000000000).
Merging ports 0, 67 (address 10'0000000000).
Merging ports 0, 68 (address 10'0000000000).
Merging ports 0, 69 (address 10'0000000000).
Merging ports 0, 70 (address 10'0000000000).
Merging ports 0, 71 (address 10'0000000000).
Merging ports 0, 72 (address 10'0000000000).
Merging ports 0, 73 (address 10'0000000000).
Merging ports 0, 74 (address 10'0000000000).
Merging ports 0, 75 (address 10'0000000000).
Merging ports 0, 76 (address 10'0000000000).
Merging ports 0, 77 (address 10'0000000000).
Merging ports 0, 78 (address 10'0000000000).
Merging ports 0, 79 (address 10'0000000000).
Merging ports 0, 80 (address 10'0000000000).
Merging ports 0, 81 (address 10'0000000000).
Merging ports 0, 82 (address 10'0000000000).
Merging ports 0, 83 (address 10'0000000000).
Merging ports 0, 84 (address 10'0000000000).
Merging ports 0, 85 (address 10'0000000000).
Merging ports 0, 86 (address 10'0000000000).
Merging ports 0, 87 (address 10'0000000000).
Merging ports 0, 88 (address 10'0000000000).
Merging ports 0, 89 (address 10'0000000000).
Merging ports 0, 90 (address 10'0000000000).
Merging ports 0, 91 (address 10'0000000000).
Merging ports 0, 92 (address 10'0000000000).
Merging ports 0, 93 (address 10'0000000000).
Merging ports 0, 94 (address 10'0000000000).
Merging ports 0, 95 (address 10'0000000000).
Merging ports 0, 96 (address 10'0000000000).
Merging ports 0, 97 (address 10'0000000000).
Merging ports 0, 98 (address 10'0000000000).
Merging ports 0, 99 (address 10'0000000000).
Merging ports 0, 100 (address 10'0000000000).
Merging ports 0, 101 (address 10'0000000000).
Merging ports 0, 102 (address 10'0000000000).
Merging ports 0, 103 (address 10'0000000000).
Merging ports 0, 104 (address 10'0000000000).
Merging ports 0, 105 (address 10'0000000000).
Merging ports 0, 106 (address 10'0000000000).
Merging ports 0, 107 (address 10'0000000000).
Merging ports 0, 108 (address 10'0000000000).
Merging ports 0, 109 (address 10'0000000000).
Merging ports 0, 110 (address 10'0000000000).
Merging ports 0, 111 (address 10'0000000000).
Merging ports 0, 112 (address 10'0000000000).
Merging ports 0, 113 (address 10'0000000000).
Merging ports 0, 114 (address 10'0000000000).
Merging ports 0, 115 (address 10'0000000000).
Merging ports 0, 116 (address 10'0000000000).
Merging ports 0, 117 (address 10'0000000000).
Merging ports 0, 118 (address 10'0000000000).
Merging ports 0, 119 (address 10'0000000000).
Merging ports 0, 120 (address 10'0000000000).
Merging ports 0, 121 (address 10'0000000000).
Merging ports 0, 122 (address 10'0000000000).
Merging ports 0, 123 (address 10'0000000000).
Merging ports 0, 124 (address 10'0000000000).
Merging ports 0, 125 (address 10'0000000000).
Merging ports 0, 126 (address 10'0000000000).
Merging ports 0, 127 (address 10'0000000000).
Merging ports 0, 128 (address 10'0000000000).
Merging ports 0, 129 (address 10'0000000000).
Merging ports 0, 130 (address 10'0000000000).
Merging ports 0, 131 (address 10'0000000000).
Merging ports 0, 132 (address 10'0000000000).
Merging ports 0, 133 (address 10'0000000000).
Merging ports 0, 134 (address 10'0000000000).
Merging ports 0, 135 (address 10'0000000000).
Merging ports 0, 136 (address 10'0000000000).
Merging ports 0, 137 (address 10'0000000000).
Merging ports 0, 138 (address 10'0000000000).
Merging ports 0, 139 (address 10'0000000000).
Merging ports 0, 140 (address 10'0000000000).
Merging ports 0, 141 (address 10'0000000000).
Merging ports 0, 142 (address 10'0000000000).
Merging ports 0, 143 (address 10'0000000000).
Merging ports 0, 144 (address 10'0000000000).
Merging ports 0, 145 (address 10'0000000000).
Merging ports 0, 146 (address 10'0000000000).
Merging ports 0, 147 (address 10'0000000000).
Merging ports 0, 148 (address 10'0000000000).
Merging ports 0, 149 (address 10'0000000000).
Merging ports 0, 150 (address 10'0000000000).
Merging ports 0, 151 (address 10'0000000000).
Merging ports 0, 152 (address 10'0000000000).
Merging ports 0, 153 (address 10'0000000000).
Merging ports 0, 154 (address 10'0000000000).
Merging ports 0, 155 (address 10'0000000000).
Merging ports 0, 156 (address 10'0000000000).
Merging ports 0, 157 (address 10'0000000000).
Merging ports 0, 158 (address 10'0000000000).
Merging ports 0, 159 (address 10'0000000000).
Merging ports 0, 160 (address 10'0000000000).
Merging ports 0, 161 (address 10'0000000000).
Merging ports 0, 162 (address 10'0000000000).
Merging ports 0, 163 (address 10'0000000000).
Merging ports 0, 164 (address 10'0000000000).
Merging ports 0, 165 (address 10'0000000000).
Merging ports 0, 166 (address 10'0000000000).
Merging ports 0, 167 (address 10'0000000000).
Merging ports 0, 168 (address 10'0000000000).
Merging ports 0, 169 (address 10'0000000000).
Merging ports 0, 170 (address 10'0000000000).
Merging ports 0, 171 (address 10'0000000000).
Merging ports 0, 172 (address 10'0000000000).
Merging ports 0, 173 (address 10'0000000000).
Merging ports 0, 174 (address 10'0000000000).
Merging ports 0, 175 (address 10'0000000000).
Merging ports 0, 176 (address 10'0000000000).
Merging ports 0, 177 (address 10'0000000000).
Merging ports 0, 178 (address 10'0000000000).
Merging ports 0, 179 (address 10'0000000000).
Merging ports 0, 180 (address 10'0000000000).
Merging ports 0, 181 (address 10'0000000000).
Merging ports 0, 182 (address 10'0000000000).
Merging ports 0, 183 (address 10'0000000000).
Merging ports 0, 184 (address 10'0000000000).
Merging ports 0, 185 (address 10'0000000000).
Merging ports 0, 186 (address 10'0000000000).
Merging ports 0, 187 (address 10'0000000000).
Merging ports 0, 188 (address 10'0000000000).
Merging ports 0, 189 (address 10'0000000000).
Merging ports 0, 190 (address 10'0000000000).
Merging ports 0, 191 (address 10'0000000000).
Merging ports 0, 192 (address 10'0000000000).
Merging ports 0, 193 (address 10'0000000000).
Merging ports 0, 194 (address 10'0000000000).
Merging ports 0, 195 (address 10'0000000000).
Merging ports 0, 196 (address 10'0000000000).
Merging ports 0, 197 (address 10'0000000000).
Merging ports 0, 198 (address 10'0000000000).
Merging ports 0, 199 (address 10'0000000000).
Merging ports 0, 200 (address 10'0000000000).
Merging ports 0, 201 (address 10'0000000000).
Merging ports 0, 202 (address 10'0000000000).
Merging ports 0, 203 (address 10'0000000000).
Merging ports 0, 204 (address 10'0000000000).
Merging ports 0, 205 (address 10'0000000000).
Merging ports 0, 206 (address 10'0000000000).
Merging ports 0, 207 (address 10'0000000000).
Merging ports 0, 208 (address 10'0000000000).
Merging ports 0, 209 (address 10'0000000000).
Merging ports 0, 210 (address 10'0000000000).
Merging ports 0, 211 (address 10'0000000000).
Merging ports 0, 212 (address 10'0000000000).
Merging ports 0, 213 (address 10'0000000000).
Merging ports 0, 214 (address 10'0000000000).
Merging ports 0, 215 (address 10'0000000000).
Merging ports 0, 216 (address 10'0000000000).
Merging ports 0, 217 (address 10'0000000000).
Merging ports 0, 218 (address 10'0000000000).
Merging ports 0, 219 (address 10'0000000000).
Merging ports 0, 220 (address 10'0000000000).
Merging ports 0, 221 (address 10'0000000000).
Merging ports 0, 222 (address 10'0000000000).
Merging ports 0, 223 (address 10'0000000000).
Merging ports 0, 224 (address 10'0000000000).
Merging ports 0, 225 (address 10'0000000000).
Merging ports 0, 226 (address 10'0000000000).
Merging ports 0, 227 (address 10'0000000000).
Merging ports 0, 228 (address 10'0000000000).
Merging ports 0, 229 (address 10'0000000000).
Merging ports 0, 230 (address 10'0000000000).
Merging ports 0, 231 (address 10'0000000000).
Merging ports 0, 232 (address 10'0000000000).
Merging ports 0, 233 (address 10'0000000000).
Merging ports 0, 234 (address 10'0000000000).
Merging ports 0, 235 (address 10'0000000000).
Merging ports 0, 236 (address 10'0000000000).
Merging ports 0, 237 (address 10'0000000000).
Merging ports 0, 238 (address 10'0000000000).
Merging ports 0, 239 (address 10'0000000000).
Merging ports 0, 240 (address 10'0000000000).
Merging ports 0, 241 (address 10'0000000000).
Merging ports 0, 242 (address 10'0000000000).
Merging ports 0, 243 (address 10'0000000000).
Merging ports 0, 244 (address 10'0000000000).
Merging ports 0, 245 (address 10'0000000000).
Merging ports 0, 246 (address 10'0000000000).
Merging ports 0, 247 (address 10'0000000000).
Merging ports 0, 248 (address 10'0000000000).
Merging ports 0, 249 (address 10'0000000000).
Merging ports 0, 250 (address 10'0000000000).
Merging ports 0, 251 (address 10'0000000000).
Merging ports 0, 252 (address 10'0000000000).
Merging ports 0, 253 (address 10'0000000000).
Merging ports 0, 254 (address 10'0000000000).
Merging ports 0, 255 (address 10'0000000000).
Merging ports 0, 256 (address 10'0000000000).
Merging ports 0, 257 (address 10'0000000000).
Merging ports 0, 258 (address 10'0000000000).
Merging ports 0, 259 (address 10'0000000000).
Merging ports 0, 260 (address 10'0000000000).
Merging ports 0, 261 (address 10'0000000000).
Merging ports 0, 262 (address 10'0000000000).
Merging ports 0, 263 (address 10'0000000000).
Merging ports 0, 264 (address 10'0000000000).
Merging ports 0, 265 (address 10'0000000000).
Merging ports 0, 266 (address 10'0000000000).
Merging ports 0, 267 (address 10'0000000000).
Merging ports 0, 268 (address 10'0000000000).
Merging ports 0, 269 (address 10'0000000000).
Merging ports 0, 270 (address 10'0000000000).
Merging ports 0, 271 (address 10'0000000000).
Merging ports 0, 272 (address 10'0000000000).
Merging ports 0, 273 (address 10'0000000000).
Merging ports 0, 274 (address 10'0000000000).
Merging ports 0, 275 (address 10'0000000000).
Merging ports 0, 276 (address 10'0000000000).
Merging ports 0, 277 (address 10'0000000000).
Merging ports 0, 278 (address 10'0000000000).
Merging ports 0, 279 (address 10'0000000000).
Merging ports 0, 280 (address 10'0000000000).
Merging ports 0, 281 (address 10'0000000000).
Merging ports 0, 282 (address 10'0000000000).
Merging ports 0, 283 (address 10'0000000000).
Merging ports 0, 284 (address 10'0000000000).
Merging ports 0, 285 (address 10'0000000000).
Merging ports 0, 286 (address 10'0000000000).
Merging ports 0, 287 (address 10'0000000000).
Merging ports 0, 288 (address 10'0000000000).
Merging ports 0, 289 (address 10'0000000000).
Merging ports 0, 290 (address 10'0000000000).
Merging ports 0, 291 (address 10'0000000000).
Merging ports 0, 292 (address 10'0000000000).
Merging ports 0, 293 (address 10'0000000000).
Merging ports 0, 294 (address 10'0000000000).
Merging ports 0, 295 (address 10'0000000000).
Merging ports 0, 296 (address 10'0000000000).
Merging ports 0, 297 (address 10'0000000000).
Merging ports 0, 298 (address 10'0000000000).
Merging ports 0, 299 (address 10'0000000000).
Merging ports 0, 300 (address 10'0000000000).
Merging ports 0, 301 (address 10'0000000000).
Merging ports 0, 302 (address 10'0000000000).
Merging ports 0, 303 (address 10'0000000000).
Merging ports 0, 304 (address 10'0000000000).
Merging ports 0, 305 (address 10'0000000000).
Merging ports 0, 306 (address 10'0000000000).
Merging ports 0, 307 (address 10'0000000000).
Merging ports 0, 308 (address 10'0000000000).
Merging ports 0, 309 (address 10'0000000000).
Merging ports 0, 310 (address 10'0000000000).
Merging ports 0, 311 (address 10'0000000000).
Merging ports 0, 312 (address 10'0000000000).
Merging ports 0, 313 (address 10'0000000000).
Merging ports 0, 314 (address 10'0000000000).
Merging ports 0, 315 (address 10'0000000000).
Merging ports 0, 316 (address 10'0000000000).
Merging ports 0, 317 (address 10'0000000000).
Merging ports 0, 318 (address 10'0000000000).
Merging ports 0, 319 (address 10'0000000000).
Merging ports 0, 320 (address 10'0000000000).
Merging ports 0, 321 (address 10'0000000000).
Merging ports 0, 322 (address 10'0000000000).
Merging ports 0, 323 (address 10'0000000000).
Merging ports 0, 324 (address 10'0000000000).
Merging ports 0, 325 (address 10'0000000000).
Merging ports 0, 326 (address 10'0000000000).
Merging ports 0, 327 (address 10'0000000000).
Merging ports 0, 328 (address 10'0000000000).
Merging ports 0, 329 (address 10'0000000000).
Merging ports 0, 330 (address 10'0000000000).
Merging ports 0, 331 (address 10'0000000000).
Merging ports 0, 332 (address 10'0000000000).
Merging ports 0, 333 (address 10'0000000000).
Merging ports 0, 334 (address 10'0000000000).
Merging ports 0, 335 (address 10'0000000000).
Merging ports 0, 336 (address 10'0000000000).
Merging ports 0, 337 (address 10'0000000000).
Merging ports 0, 338 (address 10'0000000000).
Merging ports 0, 339 (address 10'0000000000).
Merging ports 0, 340 (address 10'0000000000).
Merging ports 0, 341 (address 10'0000000000).
Merging ports 0, 342 (address 10'0000000000).
Merging ports 0, 343 (address 10'0000000000).
Merging ports 0, 344 (address 10'0000000000).
Merging ports 0, 345 (address 10'0000000000).
Merging ports 0, 346 (address 10'0000000000).
Merging ports 0, 347 (address 10'0000000000).
Merging ports 0, 348 (address 10'0000000000).
Merging ports 0, 349 (address 10'0000000000).
Merging ports 0, 350 (address 10'0000000000).
Merging ports 0, 351 (address 10'0000000000).
Merging ports 0, 352 (address 10'0000000000).
Merging ports 0, 353 (address 10'0000000000).
Merging ports 0, 354 (address 10'0000000000).
Merging ports 0, 355 (address 10'0000000000).
Merging ports 0, 356 (address 10'0000000000).
Merging ports 0, 357 (address 10'0000000000).
Merging ports 0, 358 (address 10'0000000000).
Merging ports 0, 359 (address 10'0000000000).
Merging ports 0, 360 (address 10'0000000000).
Merging ports 0, 361 (address 10'0000000000).
Merging ports 0, 362 (address 10'0000000000).
Merging ports 0, 363 (address 10'0000000000).
Merging ports 0, 364 (address 10'0000000000).
Merging ports 0, 365 (address 10'0000000000).
Merging ports 0, 366 (address 10'0000000000).
Merging ports 0, 367 (address 10'0000000000).
Merging ports 0, 368 (address 10'0000000000).
Merging ports 0, 369 (address 10'0000000000).
Merging ports 0, 370 (address 10'0000000000).
Merging ports 0, 371 (address 10'0000000000).
Merging ports 0, 372 (address 10'0000000000).
Merging ports 0, 373 (address 10'0000000000).
Merging ports 0, 374 (address 10'0000000000).
Merging ports 0, 375 (address 10'0000000000).
Merging ports 0, 376 (address 10'0000000000).
Merging ports 0, 377 (address 10'0000000000).
Merging ports 0, 378 (address 10'0000000000).
Merging ports 0, 379 (address 10'0000000000).
Merging ports 0, 380 (address 10'0000000000).
Merging ports 0, 381 (address 10'0000000000).
Merging ports 0, 382 (address 10'0000000000).
Merging ports 0, 383 (address 10'0000000000).
Merging ports 0, 384 (address 10'0000000000).
Merging ports 0, 385 (address 10'0000000000).
Merging ports 0, 386 (address 10'0000000000).
Merging ports 0, 387 (address 10'0000000000).
Merging ports 0, 388 (address 10'0000000000).
Merging ports 0, 389 (address 10'0000000000).
Merging ports 0, 390 (address 10'0000000000).
Merging ports 0, 391 (address 10'0000000000).
Merging ports 0, 392 (address 10'0000000000).
Merging ports 0, 393 (address 10'0000000000).
Merging ports 0, 394 (address 10'0000000000).
Merging ports 0, 395 (address 10'0000000000).
Merging ports 0, 396 (address 10'0000000000).
Merging ports 0, 397 (address 10'0000000000).
Merging ports 0, 398 (address 10'0000000000).
Merging ports 0, 399 (address 10'0000000000).
Merging ports 0, 400 (address 10'0000000000).
Merging ports 0, 401 (address 10'0000000000).
Merging ports 0, 402 (address 10'0000000000).
Merging ports 0, 403 (address 10'0000000000).
Merging ports 0, 404 (address 10'0000000000).
Merging ports 0, 405 (address 10'0000000000).
Merging ports 0, 406 (address 10'0000000000).
Merging ports 0, 407 (address 10'0000000000).
Merging ports 0, 408 (address 10'0000000000).
Merging ports 0, 409 (address 10'0000000000).
Merging ports 0, 410 (address 10'0000000000).
Merging ports 0, 411 (address 10'0000000000).
Merging ports 0, 412 (address 10'0000000000).
Merging ports 0, 413 (address 10'0000000000).
Merging ports 0, 414 (address 10'0000000000).
Merging ports 0, 415 (address 10'0000000000).
Merging ports 0, 416 (address 10'0000000000).
Merging ports 0, 417 (address 10'0000000000).
Merging ports 0, 418 (address 10'0000000000).
Merging ports 0, 419 (address 10'0000000000).
Merging ports 0, 420 (address 10'0000000000).
Merging ports 0, 421 (address 10'0000000000).
Merging ports 0, 422 (address 10'0000000000).
Merging ports 0, 423 (address 10'0000000000).
Merging ports 0, 424 (address 10'0000000000).
Merging ports 0, 425 (address 10'0000000000).
Merging ports 0, 426 (address 10'0000000000).
Merging ports 0, 427 (address 10'0000000000).
Merging ports 0, 428 (address 10'0000000000).
Merging ports 0, 429 (address 10'0000000000).
Merging ports 0, 430 (address 10'0000000000).
Merging ports 0, 431 (address 10'0000000000).
Merging ports 0, 432 (address 10'0000000000).
Merging ports 0, 433 (address 10'0000000000).
Merging ports 0, 434 (address 10'0000000000).
Merging ports 0, 435 (address 10'0000000000).
Merging ports 0, 436 (address 10'0000000000).
Merging ports 0, 437 (address 10'0000000000).
Merging ports 0, 438 (address 10'0000000000).
Merging ports 0, 439 (address 10'0000000000).
Merging ports 0, 440 (address 10'0000000000).
Merging ports 0, 441 (address 10'0000000000).
Merging ports 0, 442 (address 10'0000000000).
Merging ports 0, 443 (address 10'0000000000).
Merging ports 0, 444 (address 10'0000000000).
Merging ports 0, 445 (address 10'0000000000).
Merging ports 0, 446 (address 10'0000000000).
Merging ports 0, 447 (address 10'0000000000).
Merging ports 0, 448 (address 10'0000000000).
Merging ports 0, 449 (address 10'0000000000).
Merging ports 0, 450 (address 10'0000000000).
Merging ports 0, 451 (address 10'0000000000).
Merging ports 0, 452 (address 10'0000000000).
Merging ports 0, 453 (address 10'0000000000).
Merging ports 0, 454 (address 10'0000000000).
Merging ports 0, 455 (address 10'0000000000).
Merging ports 0, 456 (address 10'0000000000).
Merging ports 0, 457 (address 10'0000000000).
Merging ports 0, 458 (address 10'0000000000).
Merging ports 0, 459 (address 10'0000000000).
Merging ports 0, 460 (address 10'0000000000).
Merging ports 0, 461 (address 10'0000000000).
Merging ports 0, 462 (address 10'0000000000).
Merging ports 0, 463 (address 10'0000000000).
Merging ports 0, 464 (address 10'0000000000).
Merging ports 0, 465 (address 10'0000000000).
Merging ports 0, 466 (address 10'0000000000).
Merging ports 0, 467 (address 10'0000000000).
Merging ports 0, 468 (address 10'0000000000).
Merging ports 0, 469 (address 10'0000000000).
Merging ports 0, 470 (address 10'0000000000).
Merging ports 0, 471 (address 10'0000000000).
Merging ports 0, 472 (address 10'0000000000).
Merging ports 0, 473 (address 10'0000000000).
Merging ports 0, 474 (address 10'0000000000).
Merging ports 0, 475 (address 10'0000000000).
Merging ports 0, 476 (address 10'0000000000).
Merging ports 0, 477 (address 10'0000000000).
Merging ports 0, 478 (address 10'0000000000).
Merging ports 0, 479 (address 10'0000000000).
Merging ports 0, 480 (address 10'0000000000).
Merging ports 0, 481 (address 10'0000000000).
Merging ports 0, 482 (address 10'0000000000).
Merging ports 0, 483 (address 10'0000000000).
Merging ports 0, 484 (address 10'0000000000).
Merging ports 0, 485 (address 10'0000000000).
Merging ports 0, 486 (address 10'0000000000).
Merging ports 0, 487 (address 10'0000000000).
Merging ports 0, 488 (address 10'0000000000).
Merging ports 0, 489 (address 10'0000000000).
Merging ports 0, 490 (address 10'0000000000).
Merging ports 0, 491 (address 10'0000000000).
Merging ports 0, 492 (address 10'0000000000).
Merging ports 0, 493 (address 10'0000000000).
Merging ports 0, 494 (address 10'0000000000).
Merging ports 0, 495 (address 10'0000000000).
Merging ports 0, 496 (address 10'0000000000).
Merging ports 0, 497 (address 10'0000000000).
Merging ports 0, 498 (address 10'0000000000).
Merging ports 0, 499 (address 10'0000000000).
Merging ports 0, 500 (address 10'0000000000).
Merging ports 0, 501 (address 10'0000000000).
Merging ports 0, 502 (address 10'0000000000).
Merging ports 0, 503 (address 10'0000000000).
Merging ports 0, 504 (address 10'0000000000).
Merging ports 0, 505 (address 10'0000000000).
Merging ports 0, 506 (address 10'0000000000).
Merging ports 0, 507 (address 10'0000000000).
Merging ports 0, 508 (address 10'0000000000).
Merging ports 0, 509 (address 10'0000000000).
Merging ports 0, 510 (address 10'0000000000).
Merging ports 0, 511 (address 10'0000000000).
Merging ports 0, 512 (address 10'0000000000).
Merging ports 514, 515 (address 10'1000000010).
Merging ports 516, 517 (address 10'1000000100).
Merging ports 516, 518 (address 10'1000000100).
Merging ports 516, 519 (address 10'1000000100).
Merging ports 520, 521 (address 10'1000001000).
Merging ports 520, 522 (address 10'1000001000).
Merging ports 520, 523 (address 10'1000001000).
Merging ports 520, 524 (address 10'1000001000).
Merging ports 520, 525 (address 10'1000001000).
Merging ports 520, 526 (address 10'1000001000).
Merging ports 520, 527 (address 10'1000001000).
Merging ports 528, 529 (address 10'1000010000).
Merging ports 528, 530 (address 10'1000010000).
Merging ports 528, 531 (address 10'1000010000).
Merging ports 528, 532 (address 10'1000010000).
Merging ports 528, 533 (address 10'1000010000).
Merging ports 528, 534 (address 10'1000010000).
Merging ports 528, 535 (address 10'1000010000).
Merging ports 528, 536 (address 10'1000010000).
Merging ports 528, 537 (address 10'1000010000).
Merging ports 528, 538 (address 10'1000010000).
Merging ports 528, 539 (address 10'1000010000).
Merging ports 528, 540 (address 10'1000010000).
Merging ports 528, 541 (address 10'1000010000).
Merging ports 528, 542 (address 10'1000010000).
Merging ports 528, 543 (address 10'1000010000).
Merging ports 544, 545 (address 10'1000100000).
Merging ports 544, 546 (address 10'1000100000).
Merging ports 544, 547 (address 10'1000100000).
Merging ports 544, 548 (address 10'1000100000).
Merging ports 544, 549 (address 10'1000100000).
Merging ports 544, 550 (address 10'1000100000).
Merging ports 544, 551 (address 10'1000100000).
Merging ports 544, 552 (address 10'1000100000).
Merging ports 544, 553 (address 10'1000100000).
Merging ports 544, 554 (address 10'1000100000).
Merging ports 544, 555 (address 10'1000100000).
Merging ports 544, 556 (address 10'1000100000).
Merging ports 544, 557 (address 10'1000100000).
Merging ports 544, 558 (address 10'1000100000).
Merging ports 544, 559 (address 10'1000100000).
Merging ports 544, 560 (address 10'1000100000).
Merging ports 544, 561 (address 10'1000100000).
Merging ports 544, 562 (address 10'1000100000).
Merging ports 544, 563 (address 10'1000100000).
Merging ports 544, 564 (address 10'1000100000).
Merging ports 544, 565 (address 10'1000100000).
Merging ports 544, 566 (address 10'1000100000).
Merging ports 544, 567 (address 10'1000100000).
Merging ports 544, 568 (address 10'1000100000).
Merging ports 544, 569 (address 10'1000100000).
Merging ports 544, 570 (address 10'1000100000).
Merging ports 544, 571 (address 10'1000100000).
Merging ports 544, 572 (address 10'1000100000).
Merging ports 544, 573 (address 10'1000100000).
Merging ports 544, 574 (address 10'1000100000).
Merging ports 544, 575 (address 10'1000100000).
Merging ports 576, 577 (address 10'1001000000).
Merging ports 576, 578 (address 10'1001000000).
Merging ports 576, 579 (address 10'1001000000).
Merging ports 576, 580 (address 10'1001000000).
Merging ports 576, 581 (address 10'1001000000).
Merging ports 576, 582 (address 10'1001000000).
Merging ports 576, 583 (address 10'1001000000).
Merging ports 576, 584 (address 10'1001000000).
Merging ports 576, 585 (address 10'1001000000).
Merging ports 576, 586 (address 10'1001000000).
Merging ports 576, 587 (address 10'1001000000).
Merging ports 576, 588 (address 10'1001000000).
Merging ports 576, 589 (address 10'1001000000).
Merging ports 576, 590 (address 10'1001000000).
Merging ports 576, 591 (address 10'1001000000).
Merging ports 576, 592 (address 10'1001000000).
Merging ports 576, 593 (address 10'1001000000).
Merging ports 576, 594 (address 10'1001000000).
Merging ports 576, 595 (address 10'1001000000).
Merging ports 576, 596 (address 10'1001000000).
Merging ports 576, 597 (address 10'1001000000).
Merging ports 576, 598 (address 10'1001000000).
Merging ports 576, 599 (address 10'1001000000).
Merging ports 576, 600 (address 10'1001000000).
Merging ports 576, 601 (address 10'1001000000).
Merging ports 576, 602 (address 10'1001000000).
Merging ports 576, 603 (address 10'1001000000).
Merging ports 576, 604 (address 10'1001000000).
Merging ports 576, 605 (address 10'1001000000).
Merging ports 576, 606 (address 10'1001000000).
Merging ports 576, 607 (address 10'1001000000).
Merging ports 576, 608 (address 10'1001000000).
Merging ports 576, 609 (address 10'1001000000).
Merging ports 576, 610 (address 10'1001000000).
Merging ports 576, 611 (address 10'1001000000).
Merging ports 576, 612 (address 10'1001000000).
Merging ports 576, 613 (address 10'1001000000).
Merging ports 576, 614 (address 10'1001000000).
Merging ports 576, 615 (address 10'1001000000).
Merging ports 576, 616 (address 10'1001000000).
Merging ports 576, 617 (address 10'1001000000).
Merging ports 576, 618 (address 10'1001000000).
Merging ports 576, 619 (address 10'1001000000).
Merging ports 576, 620 (address 10'1001000000).
Merging ports 576, 621 (address 10'1001000000).
Merging ports 576, 622 (address 10'1001000000).
Merging ports 576, 623 (address 10'1001000000).
Merging ports 576, 624 (address 10'1001000000).
Merging ports 576, 625 (address 10'1001000000).
Merging ports 576, 626 (address 10'1001000000).
Merging ports 576, 627 (address 10'1001000000).
Merging ports 576, 628 (address 10'1001000000).
Merging ports 576, 629 (address 10'1001000000).
Merging ports 576, 630 (address 10'1001000000).
Merging ports 576, 631 (address 10'1001000000).
Merging ports 576, 632 (address 10'1001000000).
Merging ports 576, 633 (address 10'1001000000).
Merging ports 576, 634 (address 10'1001000000).
Merging ports 576, 635 (address 10'1001000000).
Merging ports 576, 636 (address 10'1001000000).
Merging ports 576, 637 (address 10'1001000000).
Merging ports 576, 638 (address 10'1001000000).
Merging ports 576, 639 (address 10'1001000000).
Merging ports 640, 641 (address 10'1010000000).
Merging ports 640, 642 (address 10'1010000000).
Merging ports 640, 643 (address 10'1010000000).
Merging ports 640, 644 (address 10'1010000000).
Merging ports 640, 645 (address 10'1010000000).
Merging ports 640, 646 (address 10'1010000000).
Merging ports 640, 647 (address 10'1010000000).
Merging ports 640, 648 (address 10'1010000000).
Merging ports 640, 649 (address 10'1010000000).
Merging ports 640, 650 (address 10'1010000000).
Merging ports 640, 651 (address 10'1010000000).
Merging ports 640, 652 (address 10'1010000000).
Merging ports 640, 653 (address 10'1010000000).
Merging ports 640, 654 (address 10'1010000000).
Merging ports 640, 655 (address 10'1010000000).
Merging ports 640, 656 (address 10'1010000000).
Merging ports 640, 657 (address 10'1010000000).
Merging ports 640, 658 (address 10'1010000000).
Merging ports 640, 659 (address 10'1010000000).
Merging ports 640, 660 (address 10'1010000000).
Merging ports 640, 661 (address 10'1010000000).
Merging ports 640, 662 (address 10'1010000000).
Merging ports 640, 663 (address 10'1010000000).
Merging ports 640, 664 (address 10'1010000000).
Merging ports 640, 665 (address 10'1010000000).
Merging ports 640, 666 (address 10'1010000000).
Merging ports 640, 667 (address 10'1010000000).
Merging ports 640, 668 (address 10'1010000000).
Merging ports 640, 669 (address 10'1010000000).
Merging ports 640, 670 (address 10'1010000000).
Merging ports 640, 671 (address 10'1010000000).
Merging ports 640, 672 (address 10'1010000000).
Merging ports 640, 673 (address 10'1010000000).
Merging ports 640, 674 (address 10'1010000000).
Merging ports 640, 675 (address 10'1010000000).
Merging ports 640, 676 (address 10'1010000000).
Merging ports 640, 677 (address 10'1010000000).
Merging ports 640, 678 (address 10'1010000000).
Merging ports 640, 679 (address 10'1010000000).
Merging ports 640, 680 (address 10'1010000000).
Merging ports 640, 681 (address 10'1010000000).
Merging ports 640, 682 (address 10'1010000000).
Merging ports 640, 683 (address 10'1010000000).
Merging ports 640, 684 (address 10'1010000000).
Merging ports 640, 685 (address 10'1010000000).
Merging ports 640, 686 (address 10'1010000000).
Merging ports 640, 687 (address 10'1010000000).
Merging ports 640, 688 (address 10'1010000000).
Merging ports 640, 689 (address 10'1010000000).
Merging ports 640, 690 (address 10'1010000000).
Merging ports 640, 691 (address 10'1010000000).
Merging ports 640, 692 (address 10'1010000000).
Merging ports 640, 693 (address 10'1010000000).
Merging ports 640, 694 (address 10'1010000000).
Merging ports 640, 695 (address 10'1010000000).
Merging ports 640, 696 (address 10'1010000000).
Merging ports 640, 697 (address 10'1010000000).
Merging ports 640, 698 (address 10'1010000000).
Merging ports 640, 699 (address 10'1010000000).
Merging ports 640, 700 (address 10'1010000000).
Merging ports 640, 701 (address 10'1010000000).
Merging ports 640, 702 (address 10'1010000000).
Merging ports 640, 703 (address 10'1010000000).
Merging ports 640, 704 (address 10'1010000000).
Merging ports 640, 705 (address 10'1010000000).
Merging ports 640, 706 (address 10'1010000000).
Merging ports 640, 707 (address 10'1010000000).
Merging ports 640, 708 (address 10'1010000000).
Merging ports 640, 709 (address 10'1010000000).
Merging ports 640, 710 (address 10'1010000000).
Merging ports 640, 711 (address 10'1010000000).
Merging ports 640, 712 (address 10'1010000000).
Merging ports 640, 713 (address 10'1010000000).
Merging ports 640, 714 (address 10'1010000000).
Merging ports 640, 715 (address 10'1010000000).
Merging ports 640, 716 (address 10'1010000000).
Merging ports 640, 717 (address 10'1010000000).
Merging ports 640, 718 (address 10'1010000000).
Merging ports 640, 719 (address 10'1010000000).
Merging ports 640, 720 (address 10'1010000000).
Merging ports 640, 721 (address 10'1010000000).
Merging ports 640, 722 (address 10'1010000000).
Merging ports 640, 723 (address 10'1010000000).
Merging ports 640, 724 (address 10'1010000000).
Merging ports 640, 725 (address 10'1010000000).
Merging ports 640, 726 (address 10'1010000000).
Merging ports 640, 727 (address 10'1010000000).
Merging ports 640, 728 (address 10'1010000000).
Merging ports 640, 729 (address 10'1010000000).
Merging ports 640, 730 (address 10'1010000000).
Merging ports 640, 731 (address 10'1010000000).
Merging ports 640, 732 (address 10'1010000000).
Merging ports 640, 733 (address 10'1010000000).
Merging ports 640, 734 (address 10'1010000000).
Merging ports 640, 735 (address 10'1010000000).
Merging ports 640, 736 (address 10'1010000000).
Merging ports 640, 737 (address 10'1010000000).
Merging ports 640, 738 (address 10'1010000000).
Merging ports 640, 739 (address 10'1010000000).
Merging ports 640, 740 (address 10'1010000000).
Merging ports 640, 741 (address 10'1010000000).
Merging ports 640, 742 (address 10'1010000000).
Merging ports 640, 743 (address 10'1010000000).
Merging ports 640, 744 (address 10'1010000000).
Merging ports 640, 745 (address 10'1010000000).
Merging ports 640, 746 (address 10'1010000000).
Merging ports 640, 747 (address 10'1010000000).
Merging ports 640, 748 (address 10'1010000000).
Merging ports 640, 749 (address 10'1010000000).
Merging ports 640, 750 (address 10'1010000000).
Merging ports 640, 751 (address 10'1010000000).
Merging ports 640, 752 (address 10'1010000000).
Merging ports 640, 753 (address 10'1010000000).
Merging ports 640, 754 (address 10'1010000000).
Merging ports 640, 755 (address 10'1010000000).
Merging ports 640, 756 (address 10'1010000000).
Merging ports 640, 757 (address 10'1010000000).
Merging ports 640, 758 (address 10'1010000000).
Merging ports 640, 759 (address 10'1010000000).
Merging ports 640, 760 (address 10'1010000000).
Merging ports 640, 761 (address 10'1010000000).
Merging ports 640, 762 (address 10'1010000000).
Merging ports 640, 763 (address 10'1010000000).
Merging ports 640, 764 (address 10'1010000000).
Merging ports 640, 765 (address 10'1010000000).
Merging ports 640, 766 (address 10'1010000000).
Merging ports 640, 767 (address 10'1010000000).
Merging ports 768, 769 (address 10'1100000000).
Merging ports 768, 770 (address 10'1100000000).
Merging ports 768, 771 (address 10'1100000000).
Merging ports 768, 772 (address 10'1100000000).
Merging ports 768, 773 (address 10'1100000000).
Merging ports 768, 774 (address 10'1100000000).
Merging ports 768, 775 (address 10'1100000000).
Merging ports 768, 776 (address 10'1100000000).
Merging ports 768, 777 (address 10'1100000000).
Merging ports 768, 778 (address 10'1100000000).
Merging ports 768, 779 (address 10'1100000000).
Merging ports 768, 780 (address 10'1100000000).
Merging ports 768, 781 (address 10'1100000000).
Merging ports 768, 782 (address 10'1100000000).
Merging ports 768, 783 (address 10'1100000000).
Merging ports 768, 784 (address 10'1100000000).
Merging ports 768, 785 (address 10'1100000000).
Merging ports 768, 786 (address 10'1100000000).
Merging ports 768, 787 (address 10'1100000000).
Merging ports 768, 788 (address 10'1100000000).
Merging ports 768, 789 (address 10'1100000000).
Merging ports 768, 790 (address 10'1100000000).
Merging ports 768, 791 (address 10'1100000000).
Merging ports 768, 792 (address 10'1100000000).
Merging ports 768, 793 (address 10'1100000000).
Merging ports 768, 794 (address 10'1100000000).
Merging ports 768, 795 (address 10'1100000000).
Merging ports 768, 796 (address 10'1100000000).
Merging ports 768, 797 (address 10'1100000000).
Merging ports 768, 798 (address 10'1100000000).
Merging ports 768, 799 (address 10'1100000000).
Merging ports 768, 800 (address 10'1100000000).
Merging ports 768, 801 (address 10'1100000000).
Merging ports 768, 802 (address 10'1100000000).
Merging ports 768, 803 (address 10'1100000000).
Merging ports 768, 804 (address 10'1100000000).
Merging ports 768, 805 (address 10'1100000000).
Merging ports 768, 806 (address 10'1100000000).
Merging ports 768, 807 (address 10'1100000000).
Merging ports 768, 808 (address 10'1100000000).
Merging ports 768, 809 (address 10'1100000000).
Merging ports 768, 810 (address 10'1100000000).
Merging ports 768, 811 (address 10'1100000000).
Merging ports 768, 812 (address 10'1100000000).
Merging ports 768, 813 (address 10'1100000000).
Merging ports 768, 814 (address 10'1100000000).
Merging ports 768, 815 (address 10'1100000000).
Merging ports 768, 816 (address 10'1100000000).
Merging ports 768, 817 (address 10'1100000000).
Merging ports 768, 818 (address 10'1100000000).
Merging ports 768, 819 (address 10'1100000000).
Merging ports 768, 820 (address 10'1100000000).
Merging ports 768, 821 (address 10'1100000000).
Merging ports 768, 822 (address 10'1100000000).
Merging ports 768, 823 (address 10'1100000000).
Merging ports 768, 824 (address 10'1100000000).
Merging ports 768, 825 (address 10'1100000000).
Merging ports 768, 826 (address 10'1100000000).
Merging ports 768, 827 (address 10'1100000000).
Merging ports 768, 828 (address 10'1100000000).
Merging ports 768, 829 (address 10'1100000000).
Merging ports 768, 830 (address 10'1100000000).
Merging ports 768, 831 (address 10'1100000000).
Merging ports 768, 832 (address 10'1100000000).
Merging ports 768, 833 (address 10'1100000000).
Merging ports 768, 834 (address 10'1100000000).
Merging ports 768, 835 (address 10'1100000000).
Merging ports 768, 836 (address 10'1100000000).
Merging ports 768, 837 (address 10'1100000000).
Merging ports 768, 838 (address 10'1100000000).
Merging ports 768, 839 (address 10'1100000000).
Merging ports 768, 840 (address 10'1100000000).
Merging ports 768, 841 (address 10'1100000000).
Merging ports 768, 842 (address 10'1100000000).
Merging ports 768, 843 (address 10'1100000000).
Merging ports 768, 844 (address 10'1100000000).
Merging ports 768, 845 (address 10'1100000000).
Merging ports 768, 846 (address 10'1100000000).
Merging ports 768, 847 (address 10'1100000000).
Merging ports 768, 848 (address 10'1100000000).
Merging ports 768, 849 (address 10'1100000000).
Merging ports 768, 850 (address 10'1100000000).
Merging ports 768, 851 (address 10'1100000000).
Merging ports 768, 852 (address 10'1100000000).
Merging ports 768, 853 (address 10'1100000000).
Merging ports 768, 854 (address 10'1100000000).
Merging ports 768, 855 (address 10'1100000000).
Merging ports 768, 856 (address 10'1100000000).
Merging ports 768, 857 (address 10'1100000000).
Merging ports 768, 858 (address 10'1100000000).
Merging ports 768, 859 (address 10'1100000000).
Merging ports 768, 860 (address 10'1100000000).
Merging ports 768, 861 (address 10'1100000000).
Merging ports 768, 862 (address 10'1100000000).
Merging ports 768, 863 (address 10'1100000000).
Merging ports 768, 864 (address 10'1100000000).
Merging ports 768, 865 (address 10'1100000000).
Merging ports 768, 866 (address 10'1100000000).
Merging ports 768, 867 (address 10'1100000000).
Merging ports 768, 868 (address 10'1100000000).
Merging ports 768, 869 (address 10'1100000000).
Merging ports 768, 870 (address 10'1100000000).
Merging ports 768, 871 (address 10'1100000000).
Merging ports 768, 872 (address 10'1100000000).
Merging ports 768, 873 (address 10'1100000000).
Merging ports 768, 874 (address 10'1100000000).
Merging ports 768, 875 (address 10'1100000000).
Merging ports 768, 876 (address 10'1100000000).
Merging ports 768, 877 (address 10'1100000000).
Merging ports 768, 878 (address 10'1100000000).
Merging ports 768, 879 (address 10'1100000000).
Merging ports 768, 880 (address 10'1100000000).
Merging ports 768, 881 (address 10'1100000000).
Merging ports 768, 882 (address 10'1100000000).
Merging ports 768, 883 (address 10'1100000000).
Merging ports 768, 884 (address 10'1100000000).
Merging ports 768, 885 (address 10'1100000000).
Merging ports 768, 886 (address 10'1100000000).
Merging ports 768, 887 (address 10'1100000000).
Merging ports 768, 888 (address 10'1100000000).
Merging ports 768, 889 (address 10'1100000000).
Merging ports 768, 890 (address 10'1100000000).
Merging ports 768, 891 (address 10'1100000000).
Merging ports 768, 892 (address 10'1100000000).
Merging ports 768, 893 (address 10'1100000000).
Merging ports 768, 894 (address 10'1100000000).
Merging ports 768, 895 (address 10'1100000000).
Merging ports 768, 896 (address 10'1100000000).
Merging ports 768, 897 (address 10'1100000000).
Merging ports 768, 898 (address 10'1100000000).
Merging ports 768, 899 (address 10'1100000000).
Merging ports 768, 900 (address 10'1100000000).
Merging ports 768, 901 (address 10'1100000000).
Merging ports 768, 902 (address 10'1100000000).
Merging ports 768, 903 (address 10'1100000000).
Merging ports 768, 904 (address 10'1100000000).
Merging ports 768, 905 (address 10'1100000000).
Merging ports 768, 906 (address 10'1100000000).
Merging ports 768, 907 (address 10'1100000000).
Merging ports 768, 908 (address 10'1100000000).
Merging ports 768, 909 (address 10'1100000000).
Merging ports 768, 910 (address 10'1100000000).
Merging ports 768, 911 (address 10'1100000000).
Merging ports 768, 912 (address 10'1100000000).
Merging ports 768, 913 (address 10'1100000000).
Merging ports 768, 914 (address 10'1100000000).
Merging ports 768, 915 (address 10'1100000000).
Merging ports 768, 916 (address 10'1100000000).
Merging ports 768, 917 (address 10'1100000000).
Merging ports 768, 918 (address 10'1100000000).
Merging ports 768, 919 (address 10'1100000000).
Merging ports 768, 920 (address 10'1100000000).
Merging ports 768, 921 (address 10'1100000000).
Merging ports 768, 922 (address 10'1100000000).
Merging ports 768, 923 (address 10'1100000000).
Merging ports 768, 924 (address 10'1100000000).
Merging ports 768, 925 (address 10'1100000000).
Merging ports 768, 926 (address 10'1100000000).
Merging ports 768, 927 (address 10'1100000000).
Merging ports 768, 928 (address 10'1100000000).
Merging ports 768, 929 (address 10'1100000000).
Merging ports 768, 930 (address 10'1100000000).
Merging ports 768, 931 (address 10'1100000000).
Merging ports 768, 932 (address 10'1100000000).
Merging ports 768, 933 (address 10'1100000000).
Merging ports 768, 934 (address 10'1100000000).
Merging ports 768, 935 (address 10'1100000000).
Merging ports 768, 936 (address 10'1100000000).
Merging ports 768, 937 (address 10'1100000000).
Merging ports 768, 938 (address 10'1100000000).
Merging ports 768, 939 (address 10'1100000000).
Merging ports 768, 940 (address 10'1100000000).
Merging ports 768, 941 (address 10'1100000000).
Merging ports 768, 942 (address 10'1100000000).
Merging ports 768, 943 (address 10'1100000000).
Merging ports 768, 944 (address 10'1100000000).
Merging ports 768, 945 (address 10'1100000000).
Merging ports 768, 946 (address 10'1100000000).
Merging ports 768, 947 (address 10'1100000000).
Merging ports 768, 948 (address 10'1100000000).
Merging ports 768, 949 (address 10'1100000000).
Merging ports 768, 950 (address 10'1100000000).
Merging ports 768, 951 (address 10'1100000000).
Merging ports 768, 952 (address 10'1100000000).
Merging ports 768, 953 (address 10'1100000000).
Merging ports 768, 954 (address 10'1100000000).
Merging ports 768, 955 (address 10'1100000000).
Merging ports 768, 956 (address 10'1100000000).
Merging ports 768, 957 (address 10'1100000000).
Merging ports 768, 958 (address 10'1100000000).
Merging ports 768, 959 (address 10'1100000000).
Merging ports 768, 960 (address 10'1100000000).
Merging ports 768, 961 (address 10'1100000000).
Merging ports 768, 962 (address 10'1100000000).
Merging ports 768, 963 (address 10'1100000000).
Merging ports 768, 964 (address 10'1100000000).
Merging ports 768, 965 (address 10'1100000000).
Merging ports 768, 966 (address 10'1100000000).
Merging ports 768, 967 (address 10'1100000000).
Merging ports 768, 968 (address 10'1100000000).
Merging ports 768, 969 (address 10'1100000000).
Merging ports 768, 970 (address 10'1100000000).
Merging ports 768, 971 (address 10'1100000000).
Merging ports 768, 972 (address 10'1100000000).
Merging ports 768, 973 (address 10'1100000000).
Merging ports 768, 974 (address 10'1100000000).
Merging ports 768, 975 (address 10'1100000000).
Merging ports 768, 976 (address 10'1100000000).
Merging ports 768, 977 (address 10'1100000000).
Merging ports 768, 978 (address 10'1100000000).
Merging ports 768, 979 (address 10'1100000000).
Merging ports 768, 980 (address 10'1100000000).
Merging ports 768, 981 (address 10'1100000000).
Merging ports 768, 982 (address 10'1100000000).
Merging ports 768, 983 (address 10'1100000000).
Merging ports 768, 984 (address 10'1100000000).
Merging ports 768, 985 (address 10'1100000000).
Merging ports 768, 986 (address 10'1100000000).
Merging ports 768, 987 (address 10'1100000000).
Merging ports 768, 988 (address 10'1100000000).
Merging ports 768, 989 (address 10'1100000000).
Merging ports 768, 990 (address 10'1100000000).
Merging ports 768, 991 (address 10'1100000000).
Merging ports 768, 992 (address 10'1100000000).
Merging ports 768, 993 (address 10'1100000000).
Merging ports 768, 994 (address 10'1100000000).
Merging ports 768, 995 (address 10'1100000000).
Merging ports 768, 996 (address 10'1100000000).
Merging ports 768, 997 (address 10'1100000000).
Merging ports 768, 998 (address 10'1100000000).
Merging ports 768, 999 (address 10'1100000000).
Merging ports 768, 1000 (address 10'1100000000).
Merging ports 768, 1001 (address 10'1100000000).
Merging ports 768, 1002 (address 10'1100000000).
Merging ports 768, 1003 (address 10'1100000000).
Merging ports 768, 1004 (address 10'1100000000).
Merging ports 768, 1005 (address 10'1100000000).
Merging ports 768, 1006 (address 10'1100000000).
Merging ports 768, 1007 (address 10'1100000000).
Merging ports 768, 1008 (address 10'1100000000).
Merging ports 768, 1009 (address 10'1100000000).
Merging ports 768, 1010 (address 10'1100000000).
Merging ports 768, 1011 (address 10'1100000000).
Merging ports 768, 1012 (address 10'1100000000).
Merging ports 768, 1013 (address 10'1100000000).
Merging ports 768, 1014 (address 10'1100000000).
Merging ports 768, 1015 (address 10'1100000000).
Merging ports 768, 1016 (address 10'1100000000).
Merging ports 768, 1017 (address 10'1100000000).
Merging ports 768, 1018 (address 10'1100000000).
Merging ports 768, 1019 (address 10'1100000000).
Merging ports 768, 1020 (address 10'1100000000).
Merging ports 768, 1021 (address 10'1100000000).
Merging ports 768, 1022 (address 10'1100000000).
Consolidating write ports of memory top.Core.Data_memory.ram by address:
Merging ports 1, 2 (address 10'1000000001).
Merging ports 1, 3 (address 10'1000000000).
Merging ports 1, 4 (address 10'1000000000).
Merging ports 1, 5 (address 10'1000000000).
Merging ports 1, 6 (address 10'1000000000).
Merging ports 1, 7 (address 10'1000000000).
Merging ports 1, 8 (address 10'1000000000).
Merging ports 1, 9 (address 10'1000000000).
Consolidating write ports of memory top.Core.Data_memory.ram by address:
Consolidating write ports of memory top.Core.Data_memory.ram using sat-based resource sharing:
12.24.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
Performed a total of 0 transformations.
12.24.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
12.24.10. Executing MEMORY_COLLECT pass (generating $mem cells).
12.25. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
12.26. Executing MEMORY_LIBMAP pass (mapping memories to cells).
using FF mapping for memory top.Core.Data_memory.ram
using FF mapping for memory top.Core.Instruction_memory.memory
<suppressed ~56 debug messages>
12.27. Executing TECHMAP pass (map to technology primitives).
12.27.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v' to AST representation.
Generating RTLIL representation for module `\$__TRELLIS_DPR16X4_'.
Successfully finished Verilog frontend.
12.27.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v' to AST representation.
Generating RTLIL representation for module `\$__ECP5_DP16KD_'.
Generating RTLIL representation for module `\$__ECP5_PDPW16KD_'.
Successfully finished Verilog frontend.
12.27.3. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~5 debug messages>
12.28. Executing OPT pass (performing simple optimizations).
12.28.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~186 debug messages>
12.28.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~78 debug messages>
Removed a total of 26 cells.
12.28.3. Executing OPT_DFF pass (perform DFF optimizations).
Handling always-active ARST on $flatten\Core.\Control_unit.$auto$proc_dlatch.cc:433:proc_dlatch$10665 ($dlatch) from module top (changing to const driver).
Handling always-active ARST on $flatten\Core.\Control_unit.$auto$proc_dlatch.cc:433:proc_dlatch$10525 ($dlatch) from module top (changing to const driver).
Handling always-active ARST on $flatten\Core.\Control_unit.$auto$proc_dlatch.cc:433:proc_dlatch$10595 ($dlatch) from module top (changing to const driver).
Handling never-active EN on $auto$ff.cc:266:slice$12968 ($sdffe) from module top (connecting SRST instead).
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$12968 ($dffe) from module top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$12968 ($dffe) from module top.
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$12968 ($dffe) from module top.
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$12968 ($dffe) from module top.
Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$12968 ($dffe) from module top.
Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$12968 ($dffe) from module top.
Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$12968 ($dffe) from module top.
Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$12968 ($dffe) from module top.
Setting constant 0-bit at position 8 on $auto$ff.cc:266:slice$12968 ($dffe) from module top.
Setting constant 0-bit at position 9 on $auto$ff.cc:266:slice$12968 ($dffe) from module top.
Setting constant 0-bit at position 10 on $auto$ff.cc:266:slice$12968 ($dffe) from module top.
Setting constant 0-bit at position 11 on $auto$ff.cc:266:slice$12968 ($dffe) from module top.
Setting constant 0-bit at position 12 on $auto$ff.cc:266:slice$12968 ($dffe) from module top.
Setting constant 0-bit at position 13 on $auto$ff.cc:266:slice$12968 ($dffe) from module top.
Setting constant 0-bit at position 14 on $auto$ff.cc:266:slice$12968 ($dffe) from module top.
Setting constant 0-bit at position 15 on $auto$ff.cc:266:slice$12968 ($dffe) from module top.
Setting constant 0-bit at position 16 on $auto$ff.cc:266:slice$12968 ($dffe) from module top.
Setting constant 0-bit at position 17 on $auto$ff.cc:266:slice$12968 ($dffe) from module top.
Setting constant 0-bit at position 18 on $auto$ff.cc:266:slice$12968 ($dffe) from module top.
Setting constant 0-bit at position 19 on $auto$ff.cc:266:slice$12968 ($dffe) from module top.
Setting constant 0-bit at position 20 on $auto$ff.cc:266:slice$12968 ($dffe) from module top.
Setting constant 0-bit at position 21 on $auto$ff.cc:266:slice$12968 ($dffe) from module top.
Setting constant 0-bit at position 22 on $auto$ff.cc:266:slice$12968 ($dffe) from module top.
Setting constant 0-bit at position 23 on $auto$ff.cc:266:slice$12968 ($dffe) from module top.
Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$12968 ($dffe) from module top.
Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$12968 ($dffe) from module top.
Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$12968 ($dffe) from module top.
Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$12968 ($dffe) from module top.
Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$12968 ($dffe) from module top.
Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$12968 ($dffe) from module top.
Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$12968 ($dffe) from module top.
Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$12968 ($dffe) from module top.
12.28.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 9 unused cells and 177 unused wires.
<suppressed ~10 debug messages>
12.28.5. Rerunning OPT passes. (Removed registers in this run.)
12.28.6. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~13 debug messages>
12.28.7. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
12.28.8. Executing OPT_DFF pass (perform DFF optimizations).
12.28.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 9 unused cells and 28 unused wires.
<suppressed ~21 debug messages>
12.28.10. Finished fast OPT passes.
12.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
Mapping memory \Core.Instruction_memory.memory in module \top:
created 256 $dff cells and 0 static cells of width 13.
read interface: 0 $dff and 255 $mux cells.
write interface: 0 write mux blocks.
12.30. Executing OPT pass (performing simple optimizations).
12.30.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~246 debug messages>
12.30.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
12.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
dead port 1/7 on $pmux $flatten\Core.\Alu_Control.$procmux$10463.
dead port 2/7 on $pmux $flatten\Core.\Alu_Control.$procmux$10463.
dead port 3/7 on $pmux $flatten\Core.\Alu_Control.$procmux$10463.
dead port 4/7 on $pmux $flatten\Core.\Alu_Control.$procmux$10463.
dead port 5/7 on $pmux $flatten\Core.\Alu_Control.$procmux$10463.
dead port 1/6 on $pmux $flatten\Core.\Immediate_generator.$procmux$7258.
dead port 3/6 on $pmux $flatten\Core.\Immediate_generator.$procmux$7258.
dead port 4/6 on $pmux $flatten\Core.\Immediate_generator.$procmux$7258.
dead port 5/6 on $pmux $flatten\Core.\Immediate_generator.$procmux$7258.
dead port 6/6 on $pmux $flatten\Core.\Immediate_generator.$procmux$7258.
dead port 1/32 on $pmux $flatten\Core.\registers.$procmux$7216.
dead port 2/32 on $pmux $flatten\Core.\registers.$procmux$7216.
dead port 3/32 on $pmux $flatten\Core.\registers.$procmux$7216.
dead port 4/32 on $pmux $flatten\Core.\registers.$procmux$7216.
dead port 5/32 on $pmux $flatten\Core.\registers.$procmux$7216.
dead port 6/32 on $pmux $flatten\Core.\registers.$procmux$7216.
dead port 7/32 on $pmux $flatten\Core.\registers.$procmux$7216.
dead port 8/32 on $pmux $flatten\Core.\registers.$procmux$7216.
dead port 9/32 on $pmux $flatten\Core.\registers.$procmux$7216.
dead port 10/32 on $pmux $flatten\Core.\registers.$procmux$7216.
dead port 11/32 on $pmux $flatten\Core.\registers.$procmux$7216.
dead port 12/32 on $pmux $flatten\Core.\registers.$procmux$7216.
dead port 13/32 on $pmux $flatten\Core.\registers.$procmux$7216.
dead port 14/32 on $pmux $flatten\Core.\registers.$procmux$7216.
dead port 15/32 on $pmux $flatten\Core.\registers.$procmux$7216.
dead port 16/32 on $pmux $flatten\Core.\registers.$procmux$7216.
dead port 17/32 on $pmux $flatten\Core.\registers.$procmux$7216.
dead port 18/32 on $pmux $flatten\Core.\registers.$procmux$7216.
dead port 19/32 on $pmux $flatten\Core.\registers.$procmux$7216.
dead port 20/32 on $pmux $flatten\Core.\registers.$procmux$7216.
dead port 21/32 on $pmux $flatten\Core.\registers.$procmux$7216.
dead port 22/32 on $pmux $flatten\Core.\registers.$procmux$7216.
dead port 23/32 on $pmux $flatten\Core.\registers.$procmux$7216.
dead port 24/32 on $pmux $flatten\Core.\registers.$procmux$7216.
dead port 25/32 on $pmux $flatten\Core.\registers.$procmux$7216.
dead port 26/32 on $pmux $flatten\Core.\registers.$procmux$7216.
dead port 27/32 on $pmux $flatten\Core.\registers.$procmux$7216.
dead port 28/32 on $pmux $flatten\Core.\registers.$procmux$7216.
dead port 29/32 on $pmux $flatten\Core.\registers.$procmux$7216.
dead port 31/32 on $pmux $flatten\Core.\registers.$procmux$7216.
Removed 40 multiplexer ports.
<suppressed ~5 debug messages>
12.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \top.
Consolidated identical input bits for $mux cell $memory\Core.Instruction_memory.memory$rdmux[0][7][1]$13534:
Old ports: A=13'0000001000111, B=13'x, Y=$memory\Core.Instruction_memory.memory$rdmux[0][6][0]$b$13341
New ports: A=2'01, B=2'x, Y={ $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$b$13341 [3] $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$b$13341 [0] }
New connections: { $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$b$13341 [12:4] $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$b$13341 [2:1] } = { $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$b$13341 [3] $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$b$13341 [3] $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$b$13341 [3] $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$b$13341 [3] $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$b$13341 [3] $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$b$13341 [3] $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$b$13341 [0] $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$b$13341 [3] $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$b$13341 [3] $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$b$13341 [0] $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$b$13341 [0] }
Consolidated identical input bits for $mux cell $memory\Core.Instruction_memory.memory$rdmux[0][7][0]$13531:
Old ports: A=13'1111111100000, B=13'0000000111000, Y=$memory\Core.Instruction_memory.memory$rdmux[0][6][0]$a$13340
New ports: A=2'10, B=2'01, Y={ $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$a$13340 [6] $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$a$13340 [3] }
New connections: { $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$a$13340 [12:7] $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$a$13340 [5:4] $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$a$13340 [2:0] } = { $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$a$13340 [6] $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$a$13340 [6] $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$a$13340 [6] $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$a$13340 [6] $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$a$13340 [6] $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$a$13340 [6] 1'1 $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$a$13340 [3] 3'000 }
Consolidated identical input bits for $mux cell $flatten\Core.\Alu_Control.$procmux$10463:
Old ports: A=4'0010, B=4'1000, Y=\Core.Alu.operation
New ports: A=2'01, B=2'10, Y={ \Core.Alu.operation [3] \Core.Alu.operation [1] }
New connections: { \Core.Alu.operation [2] \Core.Alu.operation [0] } = 2'00
Optimizing cells in module \top.
Consolidated identical input bits for $mux cell $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$13339:
Old ports: A=$memory\Core.Instruction_memory.memory$rdmux[0][6][0]$a$13340, B=$memory\Core.Instruction_memory.memory$rdmux[0][6][0]$b$13341, Y=$memory\Core.Instruction_memory.memory$rdmux[0][5][0]$a$13244
New ports: A={ $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$a$13340 [6] $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$a$13340 [6] 1'1 $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$a$13340 [3] 1'0 }, B={ $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$b$13341 [3] $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$b$13341 [0] $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$b$13341 [3] $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$b$13341 [3] $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$b$13341 [0] }, Y={ $memory\Core.Instruction_memory.memory$rdmux[0][5][0]$a$13244 [7:5] $memory\Core.Instruction_memory.memory$rdmux[0][5][0]$a$13244 [3] $memory\Core.Instruction_memory.memory$rdmux[0][5][0]$a$13244 [0] }
New connections: { $memory\Core.Instruction_memory.memory$rdmux[0][5][0]$a$13244 [12:8] $memory\Core.Instruction_memory.memory$rdmux[0][5][0]$a$13244 [4] $memory\Core.Instruction_memory.memory$rdmux[0][5][0]$a$13244 [2:1] } = { $memory\Core.Instruction_memory.memory$rdmux[0][5][0]$a$13244 [7] $memory\Core.Instruction_memory.memory$rdmux[0][5][0]$a$13244 [7] $memory\Core.Instruction_memory.memory$rdmux[0][5][0]$a$13244 [7] $memory\Core.Instruction_memory.memory$rdmux[0][5][0]$a$13244 [7] $memory\Core.Instruction_memory.memory$rdmux[0][5][0]$a$13244 [7] $memory\Core.Instruction_memory.memory$rdmux[0][5][0]$a$13244 [3] $memory\Core.Instruction_memory.memory$rdmux[0][5][0]$a$13244 [0] $memory\Core.Instruction_memory.memory$rdmux[0][5][0]$a$13244 [0] }
Optimizing cells in module \top.
Consolidated identical input bits for $mux cell $memory\Core.Instruction_memory.memory$rdmux[0][5][0]$13243:
Old ports: A=$memory\Core.Instruction_memory.memory$rdmux[0][5][0]$a$13244, B=13'x, Y=$memory\Core.Instruction_memory.memory$rdmux[0][4][0]$a$13196
New ports: A={ $memory\Core.Instruction_memory.memory$rdmux[0][5][0]$a$13244 [7:5] $memory\Core.Instruction_memory.memory$rdmux[0][5][0]$a$13244 [3] $memory\Core.Instruction_memory.memory$rdmux[0][5][0]$a$13244 [0] }, B=5'x, Y={ $memory\Core.Instruction_memory.memory$rdmux[0][4][0]$a$13196 [7:5] $memory\Core.Instruction_memory.memory$rdmux[0][4][0]$a$13196 [3] $memory\Core.Instruction_memory.memory$rdmux[0][4][0]$a$13196 [0] }
New connections: { $memory\Core.Instruction_memory.memory$rdmux[0][4][0]$a$13196 [12:8] $memory\Core.Instruction_memory.memory$rdmux[0][4][0]$a$13196 [4] $memory\Core.Instruction_memory.memory$rdmux[0][4][0]$a$13196 [2:1] } = { $memory\Core.Instruction_memory.memory$rdmux[0][4][0]$a$13196 [7] $memory\Core.Instruction_memory.memory$rdmux[0][4][0]$a$13196 [7] $memory\Core.Instruction_memory.memory$rdmux[0][4][0]$a$13196 [7] $memory\Core.Instruction_memory.memory$rdmux[0][4][0]$a$13196 [7] $memory\Core.Instruction_memory.memory$rdmux[0][4][0]$a$13196 [7] $memory\Core.Instruction_memory.memory$rdmux[0][4][0]$a$13196 [3] $memory\Core.Instruction_memory.memory$rdmux[0][4][0]$a$13196 [0] $memory\Core.Instruction_memory.memory$rdmux[0][4][0]$a$13196 [0] }
Optimizing cells in module \top.
Consolidated identical input bits for $mux cell $memory\Core.Instruction_memory.memory$rdmux[0][4][0]$13195:
Old ports: A=$memory\Core.Instruction_memory.memory$rdmux[0][4][0]$a$13196, B=13'x, Y=$memory\Core.Instruction_memory.memory$rdmux[0][3][0]$a$13172
New ports: A={ $memory\Core.Instruction_memory.memory$rdmux[0][4][0]$a$13196 [7:5] $memory\Core.Instruction_memory.memory$rdmux[0][4][0]$a$13196 [3] $memory\Core.Instruction_memory.memory$rdmux[0][4][0]$a$13196 [0] }, B=5'x, Y={ $memory\Core.Instruction_memory.memory$rdmux[0][3][0]$a$13172 [7:5] $memory\Core.Instruction_memory.memory$rdmux[0][3][0]$a$13172 [3] $memory\Core.Instruction_memory.memory$rdmux[0][3][0]$a$13172 [0] }
New connections: { $memory\Core.Instruction_memory.memory$rdmux[0][3][0]$a$13172 [12:8] $memory\Core.Instruction_memory.memory$rdmux[0][3][0]$a$13172 [4] $memory\Core.Instruction_memory.memory$rdmux[0][3][0]$a$13172 [2:1] } = { $memory\Core.Instruction_memory.memory$rdmux[0][3][0]$a$13172 [7] $memory\Core.Instruction_memory.memory$rdmux[0][3][0]$a$13172 [7] $memory\Core.Instruction_memory.memory$rdmux[0][3][0]$a$13172 [7] $memory\Core.Instruction_memory.memory$rdmux[0][3][0]$a$13172 [7] $memory\Core.Instruction_memory.memory$rdmux[0][3][0]$a$13172 [7] $memory\Core.Instruction_memory.memory$rdmux[0][3][0]$a$13172 [3] $memory\Core.Instruction_memory.memory$rdmux[0][3][0]$a$13172 [0] $memory\Core.Instruction_memory.memory$rdmux[0][3][0]$a$13172 [0] }
Optimizing cells in module \top.
Consolidated identical input bits for $mux cell $memory\Core.Instruction_memory.memory$rdmux[0][3][0]$13171:
Old ports: A=$memory\Core.Instruction_memory.memory$rdmux[0][3][0]$a$13172, B=13'x, Y=$memory\Core.Instruction_memory.memory$rdmux[0][2][0]$a$13160
New ports: A={ $memory\Core.Instruction_memory.memory$rdmux[0][3][0]$a$13172 [7:5] $memory\Core.Instruction_memory.memory$rdmux[0][3][0]$a$13172 [3] $memory\Core.Instruction_memory.memory$rdmux[0][3][0]$a$13172 [0] }, B=5'x, Y={ $memory\Core.Instruction_memory.memory$rdmux[0][2][0]$a$13160 [7:5] $memory\Core.Instruction_memory.memory$rdmux[0][2][0]$a$13160 [3] $memory\Core.Instruction_memory.memory$rdmux[0][2][0]$a$13160 [0] }
New connections: { $memory\Core.Instruction_memory.memory$rdmux[0][2][0]$a$13160 [12:8] $memory\Core.Instruction_memory.memory$rdmux[0][2][0]$a$13160 [4] $memory\Core.Instruction_memory.memory$rdmux[0][2][0]$a$13160 [2:1] } = { $memory\Core.Instruction_memory.memory$rdmux[0][2][0]$a$13160 [7] $memory\Core.Instruction_memory.memory$rdmux[0][2][0]$a$13160 [7] $memory\Core.Instruction_memory.memory$rdmux[0][2][0]$a$13160 [7] $memory\Core.Instruction_memory.memory$rdmux[0][2][0]$a$13160 [7] $memory\Core.Instruction_memory.memory$rdmux[0][2][0]$a$13160 [7] $memory\Core.Instruction_memory.memory$rdmux[0][2][0]$a$13160 [3] $memory\Core.Instruction_memory.memory$rdmux[0][2][0]$a$13160 [0] $memory\Core.Instruction_memory.memory$rdmux[0][2][0]$a$13160 [0] }
Optimizing cells in module \top.
Consolidated identical input bits for $mux cell $memory\Core.Instruction_memory.memory$rdmux[0][2][0]$13159:
Old ports: A=$memory\Core.Instruction_memory.memory$rdmux[0][2][0]$a$13160, B=13'x, Y=$memory\Core.Instruction_memory.memory$rdmux[0][1][0]$a$13154
New ports: A={ $memory\Core.Instruction_memory.memory$rdmux[0][2][0]$a$13160 [7:5] $memory\Core.Instruction_memory.memory$rdmux[0][2][0]$a$13160 [3] $memory\Core.Instruction_memory.memory$rdmux[0][2][0]$a$13160 [0] }, B=5'x, Y={ $memory\Core.Instruction_memory.memory$rdmux[0][1][0]$a$13154 [7:5] $memory\Core.Instruction_memory.memory$rdmux[0][1][0]$a$13154 [3] $memory\Core.Instruction_memory.memory$rdmux[0][1][0]$a$13154 [0] }
New connections: { $memory\Core.Instruction_memory.memory$rdmux[0][1][0]$a$13154 [12:8] $memory\Core.Instruction_memory.memory$rdmux[0][1][0]$a$13154 [4] $memory\Core.Instruction_memory.memory$rdmux[0][1][0]$a$13154 [2:1] } = { $memory\Core.Instruction_memory.memory$rdmux[0][1][0]$a$13154 [7] $memory\Core.Instruction_memory.memory$rdmux[0][1][0]$a$13154 [7] $memory\Core.Instruction_memory.memory$rdmux[0][1][0]$a$13154 [7] $memory\Core.Instruction_memory.memory$rdmux[0][1][0]$a$13154 [7] $memory\Core.Instruction_memory.memory$rdmux[0][1][0]$a$13154 [7] $memory\Core.Instruction_memory.memory$rdmux[0][1][0]$a$13154 [3] $memory\Core.Instruction_memory.memory$rdmux[0][1][0]$a$13154 [0] $memory\Core.Instruction_memory.memory$rdmux[0][1][0]$a$13154 [0] }
Optimizing cells in module \top.
Consolidated identical input bits for $mux cell $memory\Core.Instruction_memory.memory$rdmux[0][1][0]$13153:
Old ports: A=$memory\Core.Instruction_memory.memory$rdmux[0][1][0]$a$13154, B=13'x, Y=$memory\Core.Instruction_memory.memory$rdmux[0][0][0]$a$13151
New ports: A={ $memory\Core.Instruction_memory.memory$rdmux[0][1][0]$a$13154 [7:5] $memory\Core.Instruction_memory.memory$rdmux[0][1][0]$a$13154 [3] $memory\Core.Instruction_memory.memory$rdmux[0][1][0]$a$13154 [0] }, B=5'x, Y={ $memory\Core.Instruction_memory.memory$rdmux[0][0][0]$a$13151 [7:5] $memory\Core.Instruction_memory.memory$rdmux[0][0][0]$a$13151 [3] $memory\Core.Instruction_memory.memory$rdmux[0][0][0]$a$13151 [0] }
New connections: { $memory\Core.Instruction_memory.memory$rdmux[0][0][0]$a$13151 [12:8] $memory\Core.Instruction_memory.memory$rdmux[0][0][0]$a$13151 [4] $memory\Core.Instruction_memory.memory$rdmux[0][0][0]$a$13151 [2:1] } = { $memory\Core.Instruction_memory.memory$rdmux[0][0][0]$a$13151 [7] $memory\Core.Instruction_memory.memory$rdmux[0][0][0]$a$13151 [7] $memory\Core.Instruction_memory.memory$rdmux[0][0][0]$a$13151 [7] $memory\Core.Instruction_memory.memory$rdmux[0][0][0]$a$13151 [7] $memory\Core.Instruction_memory.memory$rdmux[0][0][0]$a$13151 [7] $memory\Core.Instruction_memory.memory$rdmux[0][0][0]$a$13151 [3] $memory\Core.Instruction_memory.memory$rdmux[0][0][0]$a$13151 [0] $memory\Core.Instruction_memory.memory$rdmux[0][0][0]$a$13151 [0] }
Optimizing cells in module \top.
Consolidated identical input bits for $mux cell $memory\Core.Instruction_memory.memory$rdmux[0][0][0]$13150:
Old ports: A=$memory\Core.Instruction_memory.memory$rdmux[0][0][0]$a$13151, B=13'x, Y={ \Core.Immediate_generator.instruction [30:24] \Core.Immediate_generator.instruction [20] \Core.Immediate_generator.instruction [16] \Core.Immediate_generator.instruction [12] \Core.Immediate_generator.instruction [10:9] \Core.Immediate_generator.instruction [7] }
New ports: A={ $memory\Core.Instruction_memory.memory$rdmux[0][0][0]$a$13151 [7:5] $memory\Core.Instruction_memory.memory$rdmux[0][0][0]$a$13151 [3] $memory\Core.Instruction_memory.memory$rdmux[0][0][0]$a$13151 [0] }, B=5'x, Y={ \Core.Immediate_generator.instruction [25:24] \Core.Immediate_generator.instruction [20] \Core.Immediate_generator.instruction [12] \Core.Immediate_generator.instruction [7] }
New connections: { \Core.Immediate_generator.instruction [30:26] \Core.Immediate_generator.instruction [16] \Core.Immediate_generator.instruction [10:9] } = { \Core.Immediate_generator.instruction [25] \Core.Immediate_generator.instruction [25] \Core.Immediate_generator.instruction [25] \Core.Immediate_generator.instruction [25] \Core.Immediate_generator.instruction [25] \Core.Immediate_generator.instruction [12] \Core.Immediate_generator.instruction [7] \Core.Immediate_generator.instruction [7] }
Optimizing cells in module \top.
Performed a total of 10 changes.
12.30.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
12.30.6. Executing OPT_DFF pass (perform DFF optimizations).
12.30.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 12 unused cells and 514 unused wires.
<suppressed ~19 debug messages>
12.30.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~39 debug messages>
12.30.9. Rerunning OPT passes. (Maybe there is more to do..)
12.30.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
dead port 1/12 on $pmux $flatten\Core.\Alu.$procmux$10478.
dead port 2/12 on $pmux $flatten\Core.\Alu.$procmux$10478.
dead port 4/12 on $pmux $flatten\Core.\Alu.$procmux$10478.
dead port 6/12 on $pmux $flatten\Core.\Alu.$procmux$10478.
dead port 7/12 on $pmux $flatten\Core.\Alu.$procmux$10478.
dead port 8/12 on $pmux $flatten\Core.\Alu.$procmux$10478.
dead port 10/12 on $pmux $flatten\Core.\Alu.$procmux$10478.
dead port 1/2 on $mux $flatten\Core.\Alu.$ternary$Pequeno-Risco-5/src/alu.v:25$10.
dead port 2/2 on $mux $flatten\Core.\Alu.$ternary$Pequeno-Risco-5/src/alu.v:25$10.
Removed 9 multiplexer ports.
<suppressed ~4 debug messages>
12.30.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \top.
Performed a total of 0 changes.
12.30.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
12.30.13. Executing OPT_DFF pass (perform DFF optimizations).
12.30.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 9 unused cells and 32 unused wires.
<suppressed ~10 debug messages>
12.30.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
12.30.16. Rerunning OPT passes. (Maybe there is more to do..)
12.30.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~4 debug messages>
12.30.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \top.
Performed a total of 0 changes.
12.30.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
12.30.20. Executing OPT_DFF pass (perform DFF optimizations).
12.30.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
12.30.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
12.30.23. Finished OPT passes. (There is nothing left to do.)
12.31. Executing TECHMAP pass (map to technology primitives).
12.31.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.
12.31.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v' to AST representation.
Generating RTLIL representation for module `\_80_ecp5_alu'.
Successfully finished Verilog frontend.
12.31.3. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $mux.
Using extmapper simplemap for cells of type $sdff.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $xor.
Using extmapper simplemap for cells of type $not.
Using template $paramod$constmap:bc9d7bfa18581e244d0e8ab08267be96cdf8c825$paramod$dce7c1188cb25d2520d170426d59301c3b73f9e7\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
Using template $paramod$6a42b6fefed750f8a1c58eab59479d960557103c\_80_ecp5_alu for cells of type $alu.
Using template $paramod$fbc7873bff55778c0b3173955b7e4bce1d9d6834\_80_ecp5_alu for cells of type $alu.
Using template $paramod$b098bc6f249c0ac91c4d6e19d54b23c285914115\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $eq.
Using extmapper simplemap for cells of type $logic_not.
Using extmapper simplemap for cells of type $sdffe.
Using extmapper simplemap for cells of type $pos.
Using extmapper simplemap for cells of type $logic_and.
Using extmapper simplemap for cells of type $logic_or.
No more expansions possible.
<suppressed ~837 debug messages>
12.32. Executing OPT pass (performing simple optimizations).
12.32.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~435 debug messages>
12.32.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~78 debug messages>
Removed a total of 26 cells.
12.32.3. Executing OPT_DFF pass (perform DFF optimizations).
12.32.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 369 unused cells and 344 unused wires.
<suppressed ~370 debug messages>
12.32.5. Finished fast OPT passes.
12.33. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
12.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
12.35. Executing TECHMAP pass (map to technology primitives).
12.35.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
Generating RTLIL representation for module `\$_ALDFF_NP_'.
Generating RTLIL representation for module `\$_ALDFF_PP_'.
Generating RTLIL representation for module `\$_ALDFFE_NPN_'.
Generating RTLIL representation for module `\$_ALDFFE_NPP_'.
Generating RTLIL representation for module `\$_ALDFFE_PPN_'.
Generating RTLIL representation for module `\$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.
12.35.2. Continuing TECHMAP pass.
Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_.
Using template \$_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_.
Using template \$_SDFFE_PP0N_ for cells of type $_SDFFE_PP0N_.
No more expansions possible.
<suppressed ~95 debug messages>
12.36. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~83 debug messages>
12.37. Executing SIMPLEMAP pass (map simple cells to gate primitives).
12.38. Executing LATTICE_GSR pass (implement FF init values).
Handling GSR in top.
12.39. Executing ATTRMVCP pass (move or copy attributes).
12.40. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 9 unused cells and 147 unused wires.
<suppressed ~10 debug messages>
12.41. Executing TECHMAP pass (map to technology primitives).
12.41.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v' to AST representation.
Generating RTLIL representation for module `\$_DLATCH_N_'.
Generating RTLIL representation for module `\$_DLATCH_P_'.
Successfully finished Verilog frontend.
12.41.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~4 debug messages>
12.42. Executing ABC9 pass.
12.42.1. Executing ABC9_OPS pass (helper functions for ABC9).
12.42.2. Executing ABC9_OPS pass (helper functions for ABC9).
12.42.3. Executing SCC pass (detecting logic loops).
Found 0 SCCs in module top.
Found 0 SCCs.
12.42.4. Executing ABC9_OPS pass (helper functions for ABC9).
12.42.5. Executing PROC pass (convert processes to netlists).
12.42.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
12.42.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.
12.42.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.
12.42.5.4. Executing PROC_INIT pass (extract init attributes).
12.42.5.5. Executing PROC_ARST pass (detect async resets in processes).
12.42.5.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
12.42.5.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
12.42.5.8. Executing PROC_DLATCH pass (convert process syncs to latches).
12.42.5.9. Executing PROC_DFF pass (convert process syncs to FFs).
12.42.5.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
12.42.5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
12.42.5.12. Executing OPT_EXPR pass (perform const folding).
12.42.6. Executing TECHMAP pass (map to technology primitives).
12.42.6.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.
12.42.6.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~160 debug messages>
12.42.7. Executing OPT pass (performing simple optimizations).
12.42.7.1. Executing OPT_EXPR pass (perform const folding).
12.42.7.2. Executing OPT_MERGE pass (detect identical cells).
Removed a total of 0 cells.
12.42.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Removed 0 multiplexer ports.
12.42.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Performed a total of 0 changes.
12.42.7.5. Executing OPT_MERGE pass (detect identical cells).
Removed a total of 0 cells.
12.42.7.6. Executing OPT_DFF pass (perform DFF optimizations).
12.42.7.7. Executing OPT_CLEAN pass (remove unused cells and wires).
12.42.7.8. Executing OPT_EXPR pass (perform const folding).
12.42.7.9. Finished OPT passes. (There is nothing left to do.)
12.42.8. Executing TECHMAP pass (map to technology primitives).
12.42.8.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_map.v' to AST representation.
Successfully finished Verilog frontend.
12.42.8.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~2 debug messages>
12.42.9. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_model.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_model.v' to AST representation.
Generating RTLIL representation for module `$__ABC9_DELAY'.
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
Generating RTLIL representation for module `$__DFF_N__$abc9_flop'.
Generating RTLIL representation for module `$__DFF_P__$abc9_flop'.
Successfully finished Verilog frontend.
12.42.10. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>
12.42.11. Executing ABC9_OPS pass (helper functions for ABC9).
12.42.12. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>
12.42.13. Executing TECHMAP pass (map to technology primitives).
12.42.13.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.
12.42.13.2. Continuing TECHMAP pass.
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $xor.
Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2.
Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4.
Using extmapper simplemap for cells of type $mux.
No more expansions possible.
<suppressed ~199 debug messages>
12.42.14. Executing OPT pass (performing simple optimizations).
12.42.14.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~18 debug messages>
12.42.14.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.
12.42.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
12.42.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \top.
Performed a total of 0 changes.
12.42.14.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
12.42.14.6. Executing OPT_DFF pass (perform DFF optimizations).
12.42.14.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 55 unused wires.
<suppressed ~1 debug messages>
12.42.14.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
12.42.14.9. Rerunning OPT passes. (Maybe there is more to do..)
12.42.14.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
12.42.14.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \top.
Performed a total of 0 changes.
12.42.14.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
12.42.14.13. Executing OPT_DFF pass (perform DFF optimizations).
12.42.14.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
12.42.14.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
12.42.14.16. Finished OPT passes. (There is nothing left to do.)
12.42.15. Executing AIGMAP pass (map logic to AIG).
Module top: replaced 18 cells with 120 new cells, skipped 39 cells.
replaced 3 cell types:
2 $_OR_
2 $_XOR_
14 $_MUX_
not replaced 3 cell types:
31 $specify2
4 $_NOT_
4 $_AND_
12.42.16. Executing AIGMAP pass (map logic to AIG).
Module top: replaced 11 cells with 77 new cells, skipped 53 cells.
replaced 1 cell types:
11 $_MUX_
not replaced 5 cell types:
11 $scopeinfo
11 $_NOT_
8 $_AND_
18 TRELLIS_FF
5 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C
12.42.16.1. Executing ABC9_OPS pass (helper functions for ABC9).
12.42.16.2. Executing ABC9_OPS pass (helper functions for ABC9).
12.42.16.3. Executing XAIGER backend.
<suppressed ~11 debug messages>
Extracted 41 AND gates and 156 wires from module `top' to a netlist network with 21 inputs and 20 outputs.
12.42.16.4. Executing ABC9_EXE pass (technology mapping using ABC9).
12.42.16.5. Executing ABC9.
Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC:
ABC: + read_lut <abc-temp-dir>/input.lut
ABC: + read_box <abc-temp-dir>/input.box
ABC: + &read <abc-temp-dir>/input.xaig
ABC: + &ps
ABC: <abc-temp-dir>/input : i/o = 21/ 20 and = 19 lev = 2 (0.57) mem = 0.00 MB box = 5 bb = 0
ABC: + &scorr
ABC: Warning: The network is combinational.
ABC: + &sweep
ABC: + &dc2
ABC: + &dch -f
ABC: + &ps
ABC: <abc-temp-dir>/input : i/o = 21/ 20 and = 2 lev = 1 (0.28) mem = 0.00 MB ch = 0 box = 1 bb = 0
ABC: + &if -W 300 -v
ABC: K = 7. Memory (bytes): Truth = 0. Cut = 60. Obj = 140. Set = 636. CutMin = no
ABC: Node = 2. Ch = 0. Total mem = 0.01 MB. Peak cut mem = 0.00 MB.
ABC: P: Del = 630.00. Ar = 2.0. Edge = 4. Cut = 2. T = 0.00 sec
ABC: P: Del = 630.00. Ar = 2.0. Edge = 4. Cut = 2. T = 0.00 sec
ABC: P: Del = 630.00. Ar = 2.0. Edge = 4. Cut = 2. T = 0.00 sec
ABC: F: Del = 630.00. Ar = 2.0. Edge = 4. Cut = 2. T = 0.00 sec
ABC: A: Del = 630.00. Ar = 2.0. Edge = 4. Cut = 2. T = 0.00 sec
ABC: A: Del = 630.00. Ar = 2.0. Edge = 4. Cut = 2. T = 0.00 sec
ABC: Total time = 0.00 sec
ABC: + &write -n <abc-temp-dir>/output.aig
ABC: + &mfs
ABC: The network is not changed by "&mfs".
ABC: + &ps -l
ABC: <abc-temp-dir>/input : i/o = 21/ 20 and = 2 lev = 1 (0.28) mem = 0.00 MB box = 1 bb = 0
ABC: Mapping (K=2) : lut = 2 edge = 4 lev = 1 (0.28) levB = 1 mem = 0.00 MB
ABC: LUT = 2 : 2=2 100.0 % Ave = 2.00
ABC: + &write -n <abc-temp-dir>/output.aig
ABC: + time
ABC: elapse: 0.00 seconds, total: 0.00 seconds
12.42.16.6. Executing AIGER frontend.
<suppressed ~98 debug messages>
Removed 1 unused cells and 49 unused wires.
12.42.16.7. Executing ABC9_OPS pass (helper functions for ABC9).
ABC RESULTS: $lut cells: 11
ABC RESULTS: $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells: 1
ABC RESULTS: input signals: 7
ABC RESULTS: output signals: 5
Removing temp directory.
12.42.17. Executing TECHMAP pass (map to technology primitives).
12.42.17.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v' to AST representation.
Generating RTLIL representation for module `\$__DFF_x__$abc9_flop'.
Generating RTLIL representation for module `\$__ABC9_SCC_BREAKER'.
Successfully finished Verilog frontend.
12.42.17.2. Continuing TECHMAP pass.
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
No more expansions possible.
<suppressed ~7 debug messages>
Removed 9 unused cells and 142 unused wires.
12.43. Executing TECHMAP pass (map to technology primitives).
12.43.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
Generating RTLIL representation for module `\$_ALDFF_NP_'.
Generating RTLIL representation for module `\$_ALDFF_PP_'.
Generating RTLIL representation for module `\$_ALDFFE_NPN_'.
Generating RTLIL representation for module `\$_ALDFFE_NPP_'.
Generating RTLIL representation for module `\$_ALDFFE_PPN_'.
Generating RTLIL representation for module `\$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Generating RTLIL representation for module `\$lut'.
Successfully finished Verilog frontend.
12.43.2. Continuing TECHMAP pass.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut.
No more expansions possible.
<suppressed ~122 debug messages>
12.44. Executing OPT_LUT_INS pass (discard unused LUT inputs).
Optimizing LUTs in top.
Removed 0 unused cells and 22 unused wires.
12.45. Executing AUTONAME pass.
Renamed 41 objects in module top (5 iterations).
<suppressed ~25 debug messages>
12.46. Executing HIERARCHY pass (managing design hierarchy).
12.46.1. Analyzing design hierarchy..
Top module: \top
12.46.2. Analyzing design hierarchy..
Top module: \top
Removed 0 unused modules.
12.47. Printing statistics.
=== top ===
Number of wires: 104
Number of wire bits: 1784
Number of public wires: 104
Number of public wire bits: 1784
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 33
$scopeinfo 11
CCU2C 1
LUT4 11
TRELLIS_FF 10
12.48. Executing CHECK pass (checking for obvious problems).
Checking module top...
Found and reported 0 problems.
12.49. Executing JSON backend.
Warnings: 1 unique messages, 1 total
End of script. Logfile hash: 3a6da4d655, CPU: user 12.39s system 0.13s, MEM: 276.92 MB peak
Yosys 0.38+120 (git sha1 1e42b4f0f, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os)
Time spent: 27% 1x opt_mem_priority (3 sec), 16% 3x proc_mux (2 sec), ...
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (NextPNR)
[Pipeline] sh
+ /eda/oss-cad-suite/bin/nextpnr-ecp5 --json ./build/out.json --write ./build/out_pnr.json --45k --lpf Pequeno-Risco-5/fpga/ecp5/pinout.lpf --textcfg ./build/out.config --package CABGA381 --speed 6 --ignore-loops --lpf-allow-unconstrained
Info: constraining clock net 'clk' to 25.00 MHz
Info: Logic utilisation before packing:
Info: Total LUT4s: 13/43848 0%
Info: logic LUTs: 11/43848 0%
Info: carry LUTs: 2/43848 0%
Info: RAM LUTs: 0/ 5481 0%
Info: RAMW LUTs: 0/10962 0%
Info: Total DFFs: 10/43848 0%
Info: Packing IOs..
Info: pin 'tx$tr_io' constrained to Bel 'X90/Y20/PIOA'.
Info: pin 'rx$tr_io' constrained to Bel 'X90/Y20/PIOC'.
Info: pin 'reset$tr_io' constrained to Bel 'X0/Y29/PIOA'.
Info: pin 'led[7]$tr_io' constrained to Bel 'X90/Y20/PIOD'.
Info: pin 'led[6]$tr_io' constrained to Bel 'X0/Y44/PIOD'.
Info: pin 'led[5]$tr_io' constrained to Bel 'X0/Y59/PIOA'.
Info: pin 'led[4]$tr_io' constrained to Bel 'X15/Y71/PIOB'.
Info: pin 'led[3]$tr_io' constrained to Bel 'X90/Y29/PIOC'.
Info: pin 'led[2]$tr_io' constrained to Bel 'X90/Y44/PIOB'.
Info: pin 'led[1]$tr_io' constrained to Bel 'X0/Y44/PIOC'.
Info: pin 'led[0]$tr_io' constrained to Bel 'X0/Y59/PIOC'.
Info: pin 'clk$tr_io' constrained to Bel 'X0/Y68/PIOC'.
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 4 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info: promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0x5d2261d5
Info: Device utilisation:
Info: TRELLIS_IO: 12/ 245 4%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 0/ 72 0%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 0/ 4 0%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 10/43848 0%
Info: TRELLIS_COMB: 19/43848 0%
Info: TRELLIS_RAMW: 0/ 5481 0%
Info: Placed 12 cells based on constraints.
Info: Creating initial analytic placement for 19 cells, random placement wirelen = 1464.
Info: at initial placer iter 0, wirelen = 524
Info: at initial placer iter 1, wirelen = 487
Info: at initial placer iter 2, wirelen = 469
Info: at initial placer iter 3, wirelen = 469
Info: Running main analytical placer, max placement attempts per cell = 10000.
Info: at iteration #1, type ALL: wirelen solved = 473, spread = 477, legal = 488; time = 0.01s
Info: HeAP Placer Time: 0.05s
Info: of which solving equations: 0.00s
Info: of which spreading cells: 0.00s
Info: of which strict legalisation: 0.00s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 7, wirelen = 488
Info: at iteration #5: temp = 0.000000, timing cost = 4, wirelen = 446
Info: at iteration #6: temp = 0.000000, timing cost = 4, wirelen = 442
Info: SA placement time 0.00s
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 454.34 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 3.30 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 12.20 ns
Info: Slack histogram:
Info: legend: * represents 1 endpoint(s)
Info: + represents [1,1) endpoint(s)
Info: [ 37799, 37872) |*
Info: [ 37872, 37945) |
Info: [ 37945, 38018) |****
Info: [ 38018, 38091) |
Info: [ 38091, 38164) |**
Info: [ 38164, 38237) |
Info: [ 38237, 38310) |
Info: [ 38310, 38383) |
Info: [ 38383, 38456) |*
Info: [ 38456, 38529) |
Info: [ 38529, 38602) |*
Info: [ 38602, 38675) |
Info: [ 38675, 38748) |*
Info: [ 38748, 38821) |
Info: [ 38821, 38894) |******
Info: [ 38894, 38967) |
Info: [ 38967, 39040) |*
Info: [ 39040, 39113) |
Info: [ 39113, 39186) |
Info: [ 39186, 39259) |*
Info: Checksum: 0x6fe2a7ef
Info: Routing globals...
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 54 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 56 | 2 51 | 2 51 | 0| 0.02 0.02|
Info: Routing complete.
Info: Router1 time 0.02s
Info: Checksum: 0x54eed6e4
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: curr total
Info: 0.5 0.5 Source Core.PC.PC_Register_TRELLIS_FF_Q.Q
Info: 0.9 1.4 Net Core.instruction_address[0] (5,44) -> (4,44)
Info: Sink Core.PC.PC_Register_CCU2C_B0$CCU2_COMB0.B
Info: Defined in:
Info: Pequeno-Risco-5/src/core.v:18.5-18.24
Info: 0.4 1.8 Source Core.PC.PC_Register_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 1.8 Net Core.PC.PC_Register_CCU2C_B0$CCU2_FCI_INT (4,44) -> (4,44)
Info: Sink Core.PC.PC_Register_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.4 2.2 Source Core.PC.PC_Register_CCU2C_B0$CCU2_COMB1.F
Info: 0.1 2.4 Net Core.PC.PC_Register_TRELLIS_FF_Q_DI[1] (4,44) -> (4,44)
Info: Sink Core.Immediate_generator.instruction_TRELLIS_FF_Q.DI
Info: Defined in:
Info: Pequeno-Risco-5/src/pc.v:24.28-24.43
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:34.26-34.27
Info: 0.0 2.4 Setup Core.Immediate_generator.instruction_TRELLIS_FF_Q.DI
Info: 1.4 ns logic, 1.0 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: curr total
Info: 0.0 0.0 Source reset$tr_io.O
Info: 1.8 1.8 Net reset$TRELLIS_IO_IN (0,29) -> (5,43)
Info: Sink Core.registers.register15_TRELLIS_FF_Q_4.LSR
Info: Defined in:
Info: Pequeno-Risco-5/fpga/ecp5/main.v:3.16-3.21
Info: 0.4 2.3 Setup Core.registers.register15_TRELLIS_FF_Q_4.LSR
Info: 0.4 ns logic, 1.8 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: curr total
Info: 0.5 0.5 Source Core.registers.register15_TRELLIS_FF_Q.Q
Info: 3.1 3.6 Net Core.registers.register15[7] (3,44) -> (35,29)
Info: Sink led_LUT4_Z_3.D
Info: Defined in:
Info: Pequeno-Risco-5/src/registers.v:29.12-29.22
Info: 0.2 3.9 Source led_LUT4_Z_3.F
Info: 3.8 7.7 Net led[7]$TRELLIS_IO_OUT (35,29) -> (90,20)
Info: Sink led[7]$tr_io.I
Info: Defined in:
Info: Pequeno-Risco-5/fpga/ecp5/main.v:6.22-6.25
Info: 0.8 ns logic, 6.9 ns routing
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 420.17 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 2.27 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 7.70 ns
Info: Slack histogram:
Info: legend: * represents 1 endpoint(s)
Info: + represents [1,1) endpoint(s)
Info: [ 37620, 37692) |*
Info: [ 37692, 37764) |
Info: [ 37764, 37836) |
Info: [ 37836, 37908) |*
Info: [ 37908, 37980) |
Info: [ 37980, 38052) |**
Info: [ 38052, 38124) |**
Info: [ 38124, 38196) |*
Info: [ 38196, 38268) |
Info: [ 38268, 38340) |
Info: [ 38340, 38412) |*
Info: [ 38412, 38484) |*
Info: [ 38484, 38556) |
Info: [ 38556, 38628) |
Info: [ 38628, 38700) |*
Info: [ 38700, 38772) |*
Info: [ 38772, 38844) |
Info: [ 38844, 38916) |
Info: [ 38916, 38988) |******
Info: [ 38988, 39060) |*
Info: Program finished normally.
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (ECPPACK)
[Pipeline] sh
+ /eda/oss-cad-suite/bin/ecppack --compress --input ./build/out.config --bit ./build/out.bit
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (openFPGAloader)
[Pipeline] sh
+ /eda/oss-cad-suite/bin/openFPGALoader -b colorlight-i9 ./build/out.bit
empty
Found 1 compatible device:
0x0d28 0x0204 0x3 DAPLink CMSIS-DAP
Open file: DONE
b3bdffff
Parse file: DONE
Enable configuration: DONE
SRAM erase: DONE
Loading: [========= ] 17.05%
Loading: [================== ] 34.10%
Loading: [========================== ] 51.15%
Loading: [=================================== ] 68.19%
Loading: [=========================================== ] 85.24%
Loading: [==================================================] 100.00%
Done
Disable configuration: DONE
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
Finished: SUCCESS
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