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Start of Pipeline - (50 sec in block)
node - (49 sec in block)
node block - (29 sec in block)
stage - (2.7 sec in block)git_clone
stage block (git_clone) - (2.3 sec in block)
sh - (0.55 sec in self)rm -Rf Pequeno-Risco-5/ build/
sh - (0.97 sec in self)git clone https://github.com/JN513/Pequeno-Risco-5.git
sh - (0.4 sec in self)cd Pequeno-Risco-5
stage - (1.9 sec in block)IVerilog
stage block (IVerilog) - (1.5 sec in block)
sh - (0.43 sec in self)mkdir -p build
sh - (0.45 sec in self) /eda/oss-cad-suite/bin/iverilog -o build/core_test.o -s core_tb Pequeno-Risco-5/src/*.v Pequeno-Risco-5/tests/core_test.v
sh - (0.41 sec in self)/eda/oss-cad-suite/bin/vvp build/core_test.o
stage - (13 sec in block)Yosys
stage block (Yosys) - (13 sec in block)
sh - (13 sec in self) /eda/oss-cad-suite/bin/yosys -p " read_verilog Pequeno-Risco-5/fpga/ecp5/main.v; read_verilog Pequeno-Risco-5/src/*.v; synth_ecp5 -json ./build/out.json -abc9 "
stage - (1.2 sec in block)NextPNR
stage block (NextPNR) - (0.83 sec in block)
sh - (0.64 sec in self) /eda/oss-cad-suite/bin/nextpnr-ecp5 --json ./build/out.json --write ./build/out_pnr.json --45k --lpf Pequeno-Risco-5/fpga/ecp5/pinout.lpf --textcfg ./build/out.config --package CABGA381 --speed 6 --ignore-loops --lpf-allow-unconstrained
stage - (1.7 sec in block)ECPPACK
stage block (ECPPACK) - (1.2 sec in block)
sh - (0.93 sec in self)/eda/oss-cad-suite/bin/ecppack --compress --input ./build/out.config --bit ./build/out.bit
stage - (7.1 sec in block)openFPGAloader
stage block (openFPGAloader) - (6.9 sec in block)
sh - (6.7 sec in self)/eda/oss-cad-suite/bin/openFPGALoader -b colorlight-i9 ./build/out.bit