Console Output
+ /eda/oss-cad-suite/bin/nextpnr-ecp5 --json ./build/out.json --write ./build/out_pnr.json --45k --lpf Pequeno-Risco-5/fpga/ecp5/pinout.lpf --textcfg ./build/out.config --package CABGA381 --speed 6 --ignore-loops --lpf-allow-unconstrained
Info: constraining clock net 'clk' to 25.00 MHz
Info: Logic utilisation before packing:
Info: Total LUT4s: 13/43848 0%
Info: logic LUTs: 11/43848 0%
Info: carry LUTs: 2/43848 0%
Info: RAM LUTs: 0/ 5481 0%
Info: RAMW LUTs: 0/10962 0%
Info: Total DFFs: 10/43848 0%
Info: Packing IOs..
Info: pin 'tx$tr_io' constrained to Bel 'X90/Y20/PIOA'.
Info: pin 'rx$tr_io' constrained to Bel 'X90/Y20/PIOC'.
Info: pin 'reset$tr_io' constrained to Bel 'X0/Y29/PIOA'.
Info: pin 'led[7]$tr_io' constrained to Bel 'X90/Y20/PIOD'.
Info: pin 'led[6]$tr_io' constrained to Bel 'X0/Y44/PIOD'.
Info: pin 'led[5]$tr_io' constrained to Bel 'X0/Y59/PIOA'.
Info: pin 'led[4]$tr_io' constrained to Bel 'X15/Y71/PIOB'.
Info: pin 'led[3]$tr_io' constrained to Bel 'X90/Y29/PIOC'.
Info: pin 'led[2]$tr_io' constrained to Bel 'X90/Y44/PIOB'.
Info: pin 'led[1]$tr_io' constrained to Bel 'X0/Y44/PIOC'.
Info: pin 'led[0]$tr_io' constrained to Bel 'X0/Y59/PIOC'.
Info: pin 'clk$tr_io' constrained to Bel 'X0/Y68/PIOC'.
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 4 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info: promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0x5d2261d5
Info: Device utilisation:
Info: TRELLIS_IO: 12/ 245 4%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 0/ 72 0%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 0/ 4 0%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 10/43848 0%
Info: TRELLIS_COMB: 19/43848 0%
Info: TRELLIS_RAMW: 0/ 5481 0%
Info: Placed 12 cells based on constraints.
Info: Creating initial analytic placement for 19 cells, random placement wirelen = 1464.
Info: at initial placer iter 0, wirelen = 524
Info: at initial placer iter 1, wirelen = 487
Info: at initial placer iter 2, wirelen = 469
Info: at initial placer iter 3, wirelen = 469
Info: Running main analytical placer, max placement attempts per cell = 10000.
Info: at iteration #1, type ALL: wirelen solved = 473, spread = 477, legal = 488; time = 0.01s
Info: HeAP Placer Time: 0.05s
Info: of which solving equations: 0.00s
Info: of which spreading cells: 0.00s
Info: of which strict legalisation: 0.00s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 7, wirelen = 488
Info: at iteration #5: temp = 0.000000, timing cost = 4, wirelen = 446
Info: at iteration #6: temp = 0.000000, timing cost = 4, wirelen = 442
Info: SA placement time 0.00s
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 454.34 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 3.30 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 12.20 ns
Info: Slack histogram:
Info: legend: * represents 1 endpoint(s)
Info: + represents [1,1) endpoint(s)
Info: [ 37799, 37872) |*
Info: [ 37872, 37945) |
Info: [ 37945, 38018) |****
Info: [ 38018, 38091) |
Info: [ 38091, 38164) |**
Info: [ 38164, 38237) |
Info: [ 38237, 38310) |
Info: [ 38310, 38383) |
Info: [ 38383, 38456) |*
Info: [ 38456, 38529) |
Info: [ 38529, 38602) |*
Info: [ 38602, 38675) |
Info: [ 38675, 38748) |*
Info: [ 38748, 38821) |
Info: [ 38821, 38894) |******
Info: [ 38894, 38967) |
Info: [ 38967, 39040) |*
Info: [ 39040, 39113) |
Info: [ 39113, 39186) |
Info: [ 39186, 39259) |*
Info: Checksum: 0x6fe2a7ef
Info: Routing globals...
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 54 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 56 | 2 51 | 2 51 | 0| 0.02 0.02|
Info: Routing complete.
Info: Router1 time 0.02s
Info: Checksum: 0x54eed6e4
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: curr total
Info: 0.5 0.5 Source Core.PC.PC_Register_TRELLIS_FF_Q.Q
Info: 0.9 1.4 Net Core.instruction_address[0] (5,44) -> (4,44)
Info: Sink Core.PC.PC_Register_CCU2C_B0$CCU2_COMB0.B
Info: Defined in:
Info: Pequeno-Risco-5/src/core.v:18.5-18.24
Info: 0.4 1.8 Source Core.PC.PC_Register_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 1.8 Net Core.PC.PC_Register_CCU2C_B0$CCU2_FCI_INT (4,44) -> (4,44)
Info: Sink Core.PC.PC_Register_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.4 2.2 Source Core.PC.PC_Register_CCU2C_B0$CCU2_COMB1.F
Info: 0.1 2.4 Net Core.PC.PC_Register_TRELLIS_FF_Q_DI[1] (4,44) -> (4,44)
Info: Sink Core.Immediate_generator.instruction_TRELLIS_FF_Q.DI
Info: Defined in:
Info: Pequeno-Risco-5/src/pc.v:24.28-24.43
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:34.26-34.27
Info: 0.0 2.4 Setup Core.Immediate_generator.instruction_TRELLIS_FF_Q.DI
Info: 1.4 ns logic, 1.0 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: curr total
Info: 0.0 0.0 Source reset$tr_io.O
Info: 1.8 1.8 Net reset$TRELLIS_IO_IN (0,29) -> (5,43)
Info: Sink Core.registers.register15_TRELLIS_FF_Q_4.LSR
Info: Defined in:
Info: Pequeno-Risco-5/fpga/ecp5/main.v:3.16-3.21
Info: 0.4 2.3 Setup Core.registers.register15_TRELLIS_FF_Q_4.LSR
Info: 0.4 ns logic, 1.8 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: curr total
Info: 0.5 0.5 Source Core.registers.register15_TRELLIS_FF_Q.Q
Info: 3.1 3.6 Net Core.registers.register15[7] (3,44) -> (35,29)
Info: Sink led_LUT4_Z_3.D
Info: Defined in:
Info: Pequeno-Risco-5/src/registers.v:29.12-29.22
Info: 0.2 3.9 Source led_LUT4_Z_3.F
Info: 3.8 7.7 Net led[7]$TRELLIS_IO_OUT (35,29) -> (90,20)
Info: Sink led[7]$tr_io.I
Info: Defined in:
Info: Pequeno-Risco-5/fpga/ecp5/main.v:6.22-6.25
Info: 0.8 ns logic, 6.9 ns routing
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 420.17 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 2.27 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 7.70 ns
Info: Slack histogram:
Info: legend: * represents 1 endpoint(s)
Info: + represents [1,1) endpoint(s)
Info: [ 37620, 37692) |*
Info: [ 37692, 37764) |
Info: [ 37764, 37836) |
Info: [ 37836, 37908) |*
Info: [ 37908, 37980) |
Info: [ 37980, 38052) |**
Info: [ 38052, 38124) |**
Info: [ 38124, 38196) |*
Info: [ 38196, 38268) |
Info: [ 38268, 38340) |
Info: [ 38340, 38412) |*
Info: [ 38412, 38484) |*
Info: [ 38484, 38556) |
Info: [ 38556, 38628) |
Info: [ 38628, 38700) |*
Info: [ 38700, 38772) |*
Info: [ 38772, 38844) |
Info: [ 38844, 38916) |
Info: [ 38916, 38988) |******
Info: [ 38988, 39060) |*
Info: Program finished normally.
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