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+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p I2SRV64-SS-v1 -b digilent_arty_a7_100t
Final configuration file generated at /var/jenkins_home/workspace/I2SRV64-SS-v1/I2SRV64-SS-v1/build_digilent_arty_a7_100t.tcl
Error executing Makefile.
ERROR: [Synth 8-9263] cannot open include file 'ltlib_v1_0_0_ver.vh' [/var/jenkins_home/workspace/I2SRV64-SS-v1/I2SRV64-SS-v1/Hardware_Source_Files/IP/JTAG_to_AXI4/hdl/ltlib_v1_0_vl_rfs.v:932]
ERROR: [Synth 8-9263] cannot open include file 'ltlib_v1_0_0_lib_fn.vh' [/var/jenkins_home/workspace/I2SRV64-SS-v1/I2SRV64-SS-v1/Hardware_Source_Files/IP/JTAG_to_AXI4/hdl/ltlib_v1_0_vl_rfs.v:953]
ERROR: [Synth 8-9263] cannot open include file 'ltlib_v1_0_0_ver.vh' [/var/jenkins_home/workspace/I2SRV64-SS-v1/I2SRV64-SS-v1/Hardware_Source_Files/IP/JTAG_to_AXI4/hdl/ltlib_v1_0_vl_rfs.v:999]
ERROR: [Synth 8-9263] cannot open include file 'ltlib_v1_0_0_lib_fn.vh' [/var/jenkins_home/workspace/I2SRV64-SS-v1/I2SRV64-SS-v1/Hardware_Source_Files/IP/JTAG_to_AXI4/hdl/ltlib_v1_0_vl_rfs.v:1013]
ERROR: [Synth 8-9263] cannot open include file 'ltlib_v1_0_0_ver.vh' [/var/jenkins_home/workspace/I2SRV64-SS-v1/I2SRV64-SS-v1/Hardware_Source_Files/IP/JTAG_to_AXI4/hdl/ltlib_v1_0_vl_rfs.v:1053]
ERROR: [Synth 8-9263] cannot open include file 'ltlib_v1_0_0_ver.vh' [/var/jenkins_home/workspace/I2SRV64-SS-v1/I2SRV64-SS-v1/Hardware_Source_Files/IP/JTAG_to_AXI4/hdl/ltlib_v1_0_vl_rfs.v:1111]
ERROR: [Synth 8-9263] cannot open include file 'ltlib_v1_0_0_ver.vh' [/var/jenkins_home/workspace/I2SRV64-SS-v1/I2SRV64-SS-v1/Hardware_Source_Files/IP/JTAG_to_AXI4/hdl/ltlib_v1_0_vl_rfs.v:1190]
ERROR: [Synth 8-9263] cannot open include file 'ltlib_v1_0_0_ver.vh' [/var/jenkins_home/workspace/I2SRV64-SS-v1/I2SRV64-SS-v1/Hardware_Source_Files/IP/JTAG_to_AXI4/hdl/ltlib_v1_0_vl_rfs.v:1284]
ERROR: [Synth 8-9263] cannot open include file 'ltlib_v1_0_0_ver.vh' [/var/jenkins_home/workspace/I2SRV64-SS-v1/I2SRV64-SS-v1/Hardware_Source_Files/IP/JTAG_to_AXI4/hdl/ltlib_v1_0_vl_rfs.v:1402]
ERROR: [Synth 8-9263] cannot open include file 'ltlib_v1_0_0_lib_fn.vh' [/var/jenkins_home/workspace/I2SRV64-SS-v1/I2SRV64-SS-v1/Hardware_Source_Files/IP/JTAG_to_AXI4/hdl/ltlib_v1_0_vl_rfs.v:1595]
ERROR: [Synth 8-9263] cannot open include file 'ltlib_v1_0_0_lib_fn.vh' [/var/jenkins_home/workspace/I2SRV64-SS-v1/I2SRV64-SS-v1/Hardware_Source_Files/IP/JTAG_to_AXI4/hdl/ltlib_v1_0_vl_rfs.v:1865]
ERROR: [Synth 8-9263] cannot open include file 'ltlib_v1_0_0_ver.vh' [/var/jenkins_home/workspace/I2SRV64-SS-v1/I2SRV64-SS-v1/Hardware_Source_Files/IP/JTAG_to_AXI4/hdl/ltlib_v1_0_vl_rfs.v:1905]
ERROR: [Synth 8-9263] cannot open include file 'ltlib_v1_0_0_ver.vh' [/var/jenkins_home/workspace/I2SRV64-SS-v1/I2SRV64-SS-v1/Hardware_Source_Files/IP/JTAG_to_AXI4/hdl/ltlib_v1_0_vl_rfs.v:2005]
ERROR: [Synth 8-5809] Error generated from encrypted envelope. [/var/jenkins_home/workspace/I2SRV64-SS-v1/I2SRV64-SS-v1/Hardware_Source_Files/IP/JTAG_to_AXI4/hdl/ltlib_v1_0_vl_rfs.v:2169]
ERROR: [Synth 8-5809] Error generated from encrypted envelope. [/var/jenkins_home/workspace/I2SRV64-SS-v1/I2SRV64-SS-v1/Hardware_Source_Files/IP/JTAG_to_AXI4/hdl/ltlib_v1_0_vl_rfs.v:2193]
ERROR: [Synth 8-5809] Error generated from encrypted envelope. [/var/jenkins_home/workspace/I2SRV64-SS-v1/I2SRV64-SS-v1/Hardware_Source_Files/IP/JTAG_to_AXI4/hdl/xsdbs_v1_0_vl_rfs.v:23]
ERROR: [Synth 8-5809] Error generated from encrypted envelope. [/var/jenkins_home/workspace/I2SRV64-SS-v1/I2SRV64-SS-v1/Hardware_Source_Files/IP/JTAG_to_AXI4/hdl/xsdbs_v1_0_vl_rfs.v:77]
ERROR: [Synth 8-9263] cannot open include file 'xsdbs_v1_0_2_i2x.vh' [/var/jenkins_home/workspace/I2SRV64-SS-v1/I2SRV64-SS-v1/Hardware_Source_Files/IP/JTAG_to_AXI4/hdl/xsdbs_v1_0_vl_rfs.v:262]
ERROR: [Synth 8-9263] cannot open include file 'xsdbs_v1_0_2_i2x.vh' [/var/jenkins_home/workspace/I2SRV64-SS-v1/I2SRV64-SS-v1/Hardware_Source_Files/IP/JTAG_to_AXI4/hdl/xsdbs_v1_0_vl_rfs.v:382]
ERROR: [Synth 8-5832] source file was generated for simulation and is not permitted as input to synthesis [/var/jenkins_home/workspace/I2SRV64-SS-v1/I2SRV64-SS-v1/Hardware_Source_Files/IP/AXI64_L2_XBar/AXI64_L2_XBar_sim_netlist.v:16]
ERROR: [Synth 8-439] module 'processorci_top' not found
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
make: *** [/eda/processor_ci/makefiles/digilent_arty_a7_100t.mk:12: digilent_arty_a7_100t.bit] Error 1

Traceback (most recent call last):
  File "/eda/processor_ci/main.py", line 135, in <module>
    main(
  File "/eda/processor_ci/main.py", line 82, in main
    build(build_file_path, board_name, toolchain_path)
  File "/eda/processor_ci/core/fpga.py", line 307, in build
    raise subprocess.CalledProcessError(process.returncode, 'make')
subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2.