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Start of Pipeline - (13 min in block)
node - (13 min in block)
node block - (5 min 47 sec in block)
stage - (13 sec in block)Git Clone
stage block (Git Clone) - (13 sec in block)
sh - (1.1 sec in self)rm -rf I2SRV32-V-v1
sh - (11 sec in self)git clone --recursive --depth=1 https://github.com/RClabiisc/I2SRV32-V-v1 I2SRV32-V-v1
stage - (1.4 sec in block)Simulation
stage block (Simulation) - (0.95 sec in block)
dir - (0.59 sec in block)I2SRV32-V-v1
dir block - (0.32 sec in block)
echo - (0.11 sec in self)simulation not supported for mixed VHDL and Verilog files
stage - (2 sec in block)Utilities
stage block (Utilities) - (1.6 sec in block)
dir - (1.1 sec in block)I2SRV32-V-v1
dir block - (0.87 sec in block)
sh - (0.67 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config.json -o /jenkins/processor_ci_utils/labels
stage - (5 min 28 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (5 min 27 sec in block)
parallel - (5 min 26 sec in block)
parallel block (Branch: colorlight_i9) - (59 ms in block)
stage - (2 min 18 sec in block)colorlight_i9
stage block (colorlight_i9) - (2 min 18 sec in block)
lock - (2 min 17 sec in block)colorlight_i9
lock block - (4.8 sec in block)
stage - (2.6 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (2 sec in block)
dir - (1.3 sec in block)I2SRV32-V-v1
dir block - (0.97 sec in block)
echo - (0.15 sec in self)Starting synthesis for FPGA colorlight_i9.
sh - (0.46 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p I2SRV32-V-v1 -b colorlight_i9
stage - (0.95 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (0.38 sec in block)
getContext - (0.17 sec in self)
stage - (0.69 sec in block)Test colorlight_i9
stage block (Test colorlight_i9) - (0.37 sec in block)
getContext - (0.15 sec in self)
parallel block (Branch: digilent_arty_a7_100t) - (5 min 25 sec in block)
stage - (5 min 25 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (5 min 24 sec in block)
lock - (5 min 23 sec in block)digilent_arty_a7_100t
lock block - (46 sec in block)
stage - (42 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (41 sec in block)
dir - (40 sec in block)I2SRV32-V-v1
dir block - (39 sec in block)
echo - (0.33 sec in self)Starting synthesis for FPGA digilent_arty_a7_100t.
sh - (39 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p I2SRV32-V-v1 -b digilent_arty_a7_100t
stage - (1.8 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (0.7 sec in block)
getContext - (0.32 sec in self)
stage - (1.2 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (0.7 sec in block)
getContext - (0.31 sec in self)
stage - (0.9 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.62 sec in block)
junit - (0.27 sec in self)**/test-reports/*.xml