Console Output

+ /eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s hazard3_core -I hdl/ hdl/hazard3_core.v hdl/hazard3_cpu_1port.v hdl/hazard3_cpu_2port.v hdl/hazard3_csr.v hdl/hazard3_decode.v hdl/hazard3_frontend.v hdl/hazard3_instr_decompress.v hdl/hazard3_irq_ctrl.v hdl/hazard3_pmp.v hdl/hazard3_power_ctrl.v hdl/hazard3_regfile_1w2r.v hdl/hazard3_triggers.v hdl/arith/hazard3_alu.v hdl/arith/hazard3_branchcmp.v hdl/arith/hazard3_mul_fast.v hdl/arith/hazard3_muldiv_seq.v hdl/arith/hazard3_onehot_encode.v hdl/arith/hazard3_onehot_priority.v hdl/arith/hazard3_onehot_priority_dynamic.v hdl/arith/hazard3_priority_encode.v hdl/arith/hazard3_shift_barrel.v hdl/debug/cdc/hazard3_apb_async_bridge.v hdl/debug/cdc/hazard3_reset_sync.v hdl/debug/cdc/hazard3_sync_1bit.v hdl/debug/dm/hazard3_dm.v hdl/debug/dm/hazard3_sbus_to_ahb.v hdl/debug/dtm/hazard3_ecp5_jtag_dtm.v hdl/debug/dtm/hazard3_jtag_dtm.v hdl/debug/dtm/hazard3_jtag_dtm_core.v
hdl/hazard3_triggers.v:55: parameter declarations are not permitted in generate blocks