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Start of Pipeline - (57 sec in block)
node - (53 sec in block)
node block - (53 sec in block)
stage - (1.4 sec in block)Git Clone
stage block (Git Clone) - (0.74 sec in block)
getContext - (0.22 sec in self)
stage - (1.3 sec in block)Simulation
stage block (Simulation) - (0.39 sec in block)
getContext - (0.17 sec in self)
stage - (2.1 sec in block)Utilities
stage block (Utilities) - (0.91 sec in block)
getContext - (0.41 sec in self)
stage - (45 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (44 sec in block)
parallel - (43 sec in block)
parallel block (Branch: colorlight_i9) - (0.11 sec in block)
stage - (42 sec in block)colorlight_i9
stage block (colorlight_i9) - (41 sec in block)
lock - (40 sec in block)colorlight_i9
lock block - (39 sec in block)
stage - (6.3 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (4.9 sec in block)
dir - (3.3 sec in block)Grande-Risco-5
dir block - (2.7 sec in block)
echo - (0.41 sec in self)Starting synthesis for FPGA colorlight_i9.
sh - (1.4 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p Grande-Risco-5 -b colorlight_i9
stage - (26 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (25 sec in block)
dir - (24 sec in block)Grande-Risco-5
dir block - (23 sec in block)
echo - (0.34 sec in self)Flashing FPGA colorlight_i9.
sh - (22 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p Grande-Risco-5 -b colorlight_i9 -l
stage - (4.4 sec in block)Test colorlight_i9
stage block (Test colorlight_i9) - (3.8 sec in block)
echo - (0.48 sec in self)Testing FPGA colorlight_i9.
dir - (2.3 sec in block)Grande-Risco-5
dir block - (1.7 sec in block)
sh - (0.71 sec in self)echo "Test for FPGA in /dev/ttyACM0"
sh - (0.63 sec in self)python3 /eda/processor_ci_tests/main.py -b 115200 -s 2 -c /eda/processor_ci_tests/config.json --p /dev/ttyACM0 -m rv32i -k 0x434F4C4F
parallel block (Branch: digilent_arty_a7_100t) - (25 sec in block)
stage - (24 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (23 sec in block)
lock - (21 sec in block)digilent_arty_a7_100t
lock block - (20 sec in block)
stage - (6.3 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (4.6 sec in block)
dir - (3.2 sec in block)Grande-Risco-5
dir block - (2.4 sec in block)
echo - (0.36 sec in self)Starting synthesis for FPGA digilent_arty_a7_100t.
sh - (0.77 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p Grande-Risco-5 -b digilent_arty_a7_100t
stage - (8.1 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (7.1 sec in block)
dir - (5.8 sec in block)Grande-Risco-5
dir block - (5.3 sec in block)
echo - (0.38 sec in self)Flashing FPGA digilent_arty_a7_100t.
sh - (4 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p Grande-Risco-5 -b digilent_arty_a7_100t -l
stage - (4.3 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (3.7 sec in block)
echo - (0.4 sec in self)Testing FPGA digilent_arty_a7_100t.
dir - (2.4 sec in block)Grande-Risco-5
dir block - (1.7 sec in block)
sh - (0.67 sec in self)echo "Test for FPGA in /dev/ttyUSB1"
sh - (0.68 sec in self)python3 /eda/processor_ci_tests/main.py -b 115200 -s 2 -c /eda/processor_ci_tests/config.json --p /dev/ttyUSB1 -m rv32i -k 0x41525459
stage - (1.5 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (1.1 sec in block)
junit - (0.55 sec in self)**/test-reports/*.xml