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Start of Pipeline - (39 sec in block)
node - (38 sec in block)
node block - (37 sec in block)
stage - (1.1 sec in block)Git Clone
stage block (Git Clone) - (0.37 sec in block)
getContext - (0.16 sec in self)
stage - (0.96 sec in block)Simulation
stage block (Simulation) - (0.38 sec in block)
getContext - (0.17 sec in self)
stage - (0.98 sec in block)Utilities
stage block (Utilities) - (0.38 sec in block)
getContext - (0.16 sec in self)
stage - (33 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (32 sec in block)
parallel - (31 sec in block)
parallel block (Branch: colorlight_i9) - (58 ms in block)
stage - (30 sec in block)colorlight_i9
stage block (colorlight_i9) - (30 sec in block)
lock - (29 sec in block)colorlight_i9
lock block - (29 sec in block)
stage - (3 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (2.1 sec in block)
dir - (1.4 sec in block)Grande-Risco-5
dir block - (1.1 sec in block)
echo - (0.15 sec in self)Starting synthesis for FPGA colorlight_i9.
sh - (0.62 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p Grande-Risco-5 -b colorlight_i9
stage - (20 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (19 sec in block)
dir - (19 sec in block)Grande-Risco-5
dir block - (18 sec in block)
echo - (0.17 sec in self)Flashing FPGA colorlight_i9.
sh - (18 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p Grande-Risco-5 -b colorlight_i9 -l
stage - (4.9 sec in block)Test colorlight_i9
stage block (Test colorlight_i9) - (4.6 sec in block)
echo - (0.25 sec in self)Testing FPGA colorlight_i9.
dir - (3.9 sec in block)Grande-Risco-5
dir block - (3.5 sec in block)
sh - (0.52 sec in self)echo "Test for FPGA in /dev/ttyACM0"
sh - (2.5 sec in self)python3 /eda/processor_ci_tests/main.py -b 115200 -s 2 -c /eda/processor_ci_tests/config.json --p /dev/ttyACM0 -m rv32i -k 0x434F4C4F
parallel block (Branch: digilent_arty_a7_100t) - (14 sec in block)
stage - (14 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (13 sec in block)
lock - (12 sec in block)digilent_arty_a7_100t
lock block - (12 sec in block)
stage - (3 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (2.4 sec in block)
dir - (1.7 sec in block)Grande-Risco-5
dir block - (1.3 sec in block)
echo - (0.17 sec in self)Starting synthesis for FPGA digilent_arty_a7_100t.
sh - (0.7 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p Grande-Risco-5 -b digilent_arty_a7_100t
stage - (5.6 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (5.1 sec in block)
dir - (4.5 sec in block)Grande-Risco-5
dir block - (4.3 sec in block)
echo - (0.15 sec in self)Flashing FPGA digilent_arty_a7_100t.
sh - (3.6 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p Grande-Risco-5 -b digilent_arty_a7_100t -l
stage - (2.7 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (2.3 sec in block)
echo - (0.2 sec in self)Testing FPGA digilent_arty_a7_100t.
dir - (1.7 sec in block)Grande-Risco-5
dir block - (1.4 sec in block)
sh - (0.48 sec in self)echo "Test for FPGA in /dev/ttyUSB1"
sh - (0.71 sec in self)python3 /eda/processor_ci_tests/main.py -b 115200 -s 2 -c /eda/processor_ci_tests/config.json --p /dev/ttyUSB1 -m rv32i -k 0x41525459
stage - (0.8 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.54 sec in block)
junit - (0.28 sec in self)**/test-reports/*.xml