WARNING: [Synth 8-7129] Port MSTATUS[2][18] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[2][17] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[2][16] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[2][15] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[2][14] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[2][13] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[2][12] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[2][11] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[2][10] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[2][9] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[2][8] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[2][7] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[2][6] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[2][5] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[2][4] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[1][31] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[1][30] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[1][29] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[1][28] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[1][27] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[1][26] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[1][25] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[1][24] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[1][23] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[1][22] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[1][21] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[1][20] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[1][19] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[1][18] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[1][17] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[1][16] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[1][15] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[1][14] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[1][13] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[1][12] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[1][11] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[1][10] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[1][9] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[1][8] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[1][7] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[1][6] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[1][5] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[1][4] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[0][31] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[0][30] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[0][29] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[0][28] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[0][27] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[0][26] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[0][25] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[0][24] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[0][23] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[0][22] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[0][21] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[0][20] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[0][19] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[0][18] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[0][17] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[0][16] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[0][15] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[0][14] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[0][13] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[0][12] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[0][11] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[0][10] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[0][9] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[0][8] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[0][7] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[0][6] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[0][5] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MSTATUS[0][4] in module Pipeline is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[2][31] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[2][30] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[2][29] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[2][28] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[2][27] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[2][26] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[2][25] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[2][24] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[2][23] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[2][22] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[2][21] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[2][20] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[2][19] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[2][18] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[2][17] in module Debug_UNIT is either unconnected or has no load
WARNING: [Synth 8-7129] Port MIP[2][16] in module Debug_UNIT is either unconnected or has no load
INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 2206.715 ; gain = 577.652 ; free physical = 583 ; free virtual = 27342
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2218.590 ; gain = 589.527 ; free physical = 582 ; free virtual = 27342
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2218.590 ; gain = 589.527 ; free physical = 582 ; free virtual = 27342
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00.23 ; elapsed = 00:00:00.23 . Memory (MB): peak = 2218.590 ; gain = 0.000 ; free physical = 580 ; free virtual = 27339
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]
WARNING: [Vivado 12-507] No nets matched 'sck_IBUF'. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
Finished Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/processorci_top_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/processorci_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2359.340 ; gain = 0.000 ; free physical = 564 ; free virtual = 27324
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2359.375 ; gain = 0.000 ; free physical = 564 ; free virtual = 27324
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:20 ; elapsed = 00:00:19 . Memory (MB): peak = 2359.375 ; gain = 730.312 ; free physical = 563 ; free virtual = 27322
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7a100tcsg324-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:20 ; elapsed = 00:00:19 . Memory (MB): peak = 2359.375 ; gain = 730.312 ; free physical = 563 ; free virtual = 27322
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:20 ; elapsed = 00:00:19 . Memory (MB): peak = 2359.375 ; gain = 730.312 ; free physical = 563 ; free virtual = 27322
---------------------------------------------------------------------------------
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_rx'
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tx'
INFO: [Synth 8-802] inferred FSM for state register 'state_read_reg' in module 'UART'
INFO: [Synth 8-802] inferred FSM for state register 'state_write_reg' in module 'UART'
INFO: [Synth 8-802] inferred FSM for state register 'tx_read_fifo_state_reg' in module 'UART'
INFO: [Synth 8-802] inferred FSM for state register 'state_DBU_reg' in module 'Debug_UNIT'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'ResetBootSystem'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FSM_IDLE | 00 | 000
FSM_START | 11 | 001
FSM_RECV | 10 | 010
FSM_STOP | 01 | 011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_rx'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FSM_IDLE | 00 | 000
FSM_START | 11 | 001
FSM_SEND | 10 | 010
FSM_STOP | 01 | 011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tx'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
IDLE | 000 | 0000
READ | 001 | 0001
COPY_READ_BUFFER | 010 | 0100
WB | 011 | 0010
FINISH | 100 | 0011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_read_reg' using encoding 'sequential' in module 'UART'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
IDLE | 000 | 0000
COPY_WRITE_BUFFER | 001 | 0100
WRITE | 010 | 0101
WB | 011 | 0010
FINISH | 100 | 0011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_write_reg' using encoding 'sequential' in module 'UART'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
TX_FIFO_IDLE | 0001 | 00
TX_FIFO_READ_FIFO | 0010 | 01
TX_FIFO_WRITE_TX | 0100 | 10
TX_FIFO_WAIT | 1000 | 11
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'tx_read_fifo_state_reg' using encoding 'one-hot' in module 'UART'
WARNING: [Synth 8-327] inferring latch for variable 'pc_update_logic[2].taken_branch_pc_lat_internal_reg[2]' [/var/jenkins_home/workspace/F03x/F03x/klessydra-f0-3th/RTL-Program_Counter_unit_TMR.vhd:189]
WARNING: [Synth 8-327] inferring latch for variable 'pc_update_logic[1].taken_branch_pc_lat_internal_reg[1]' [/var/jenkins_home/workspace/F03x/F03x/klessydra-f0-3th/RTL-Program_Counter_unit_TMR.vhd:313]
WARNING: [Synth 8-327] inferring latch for variable 'pc_update_logic[0].taken_branch_pc_lat_internal_reg[0]' [/var/jenkins_home/workspace/F03x/F03x/klessydra-f0-3th/RTL-Program_Counter_unit_TMR.vhd:313]
WARNING: [Synth 8-327] inferring latch for variable 'pc_update_logic[0].wfi_condition_pending_wire_reg' [/var/jenkins_home/workspace/F03x/F03x/klessydra-f0-3th/RTL-Program_Counter_unit_TMR.vhd:277]
WARNING: [Synth 8-327] inferring latch for variable 'pc_update_logic[1].wfi_condition_pending_wire_reg' [/var/jenkins_home/workspace/F03x/F03x/klessydra-f0-3th/RTL-Program_Counter_unit_TMR.vhd:277]
WARNING: [Synth 8-327] inferring latch for variable 'pc_update_logic[2].wfi_condition_pending_wire_reg' [/var/jenkins_home/workspace/F03x/F03x/klessydra-f0-3th/RTL-Program_Counter_unit_TMR.vhd:277]
WARNING: [Synth 8-327] inferring latch for variable 'CSR_updating_logic[0].trap_hndlr_reg' [/var/jenkins_home/workspace/F03x/F03x/klessydra-f0-3th/RTL-CSR_Unit_TMR.vhd:290]
WARNING: [Synth 8-327] inferring latch for variable 'CSR_updating_logic[1].trap_hndlr_reg' [/var/jenkins_home/workspace/F03x/F03x/klessydra-f0-3th/RTL-CSR_Unit_TMR.vhd:290]
WARNING: [Synth 8-327] inferring latch for variable 'CSR_updating_logic[2].trap_hndlr_reg' [/var/jenkins_home/workspace/F03x/F03x/klessydra-f0-3th/RTL-CSR_Unit_TMR.vhd:290]
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
running | 000 | 000
single_step_req | 001 | 011
halt_req | 010 | 001
halt | 011 | 010
single_step | 100 | 100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_DBU_reg' using encoding 'sequential' in module 'Debug_UNIT'
WARNING: [Synth 8-327] inferring latch for variable 'fsm_IE_comb.PC_offset_wires_reg[2]' [/var/jenkins_home/workspace/F03x/F03x/klessydra-f0-3th/RTL-Processing_Pipeline_TMR.vhd:2273]
WARNING: [Synth 8-327] inferring latch for variable 'fsm_IE_comb.PC_offset_wires_reg[1]' [/var/jenkins_home/workspace/F03x/F03x/klessydra-f0-3th/RTL-Processing_Pipeline_TMR.vhd:2273]
WARNING: [Synth 8-327] inferring latch for variable 'fsm_IE_comb.PC_offset_wires_reg[0]' [/var/jenkins_home/workspace/F03x/F03x/klessydra-f0-3th/RTL-Processing_Pipeline_TMR.vhd:2273]
WARNING: [Synth 8-327] inferring latch for variable 'harc_ID_lat_reg' [/var/jenkins_home/workspace/F03x/F03x/klessydra-f0-3th/RTL-Processing_Pipeline_TMR.vhd:1141]
WARNING: [Synth 8-327] inferring latch for variable 'instr_word_ID_lat_reg' [/var/jenkins_home/workspace/F03x/F03x/klessydra-f0-3th/RTL-Processing_Pipeline_TMR.vhd:1139]
WARNING: [Synth 8-327] inferring latch for variable 'pc_ID_lat_reg' [/var/jenkins_home/workspace/F03x/F03x/klessydra-f0-3th/RTL-Processing_Pipeline_TMR.vhd:1140]
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
INIT | 001 | 00
RESET_COUNTER | 010 | 01
IDLE | 100 | 10
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'ResetBootSystem'
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:28 ; elapsed = 00:00:27 . Memory (MB): peak = 2359.375 ; gain = 730.312 ; free physical = 559 ; free virtual = 27321
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 64 Bit Adders := 2
2 Input 32 Bit Adders := 42
3 Input 32 Bit Adders := 1
2 Input 24 Bit Adders := 2
2 Input 10 Bit Adders := 2
2 Input 8 Bit Adders := 1
2 Input 5 Bit Adders := 1
2 Input 4 Bit Adders := 4
2 Input 3 Bit Adders := 6
2 Input 2 Bit Adders := 4
+---XORs :
2 Input 32 Bit XORs := 2
+---Registers :
64 Bit Registers := 2
53 Bit Registers := 1
32 Bit Registers := 162
24 Bit Registers := 4
12 Bit Registers := 1
10 Bit Registers := 2
9 Bit Registers := 1
8 Bit Registers := 11
6 Bit Registers := 1
5 Bit Registers := 1
4 Bit Registers := 2
3 Bit Registers := 3
2 Bit Registers := 8
1 Bit Registers := 72
+---RAMs :
64K Bit (2048 X 32 bit) RAMs := 1
32K Bit (1024 X 32 bit) RAMs := 1
64 Bit (8 X 8 bit) RAMs := 2
+---Muxes :
4 Input 64 Bit Muxes := 1
2 Input 64 Bit Muxes := 1
48 Input 64 Bit Muxes := 2
2 Input 53 Bit Muxes := 16
13 Input 53 Bit Muxes := 1
6 Input 52 Bit Muxes := 2
2 Input 52 Bit Muxes := 4
4 Input 52 Bit Muxes := 1
7 Input 52 Bit Muxes := 1
10 Input 52 Bit Muxes := 2
3 Input 52 Bit Muxes := 1
2 Input 32 Bit Muxes := 592
3 Input 32 Bit Muxes := 89
8 Input 32 Bit Muxes := 10
4 Input 32 Bit Muxes := 67
7 Input 32 Bit Muxes := 5
18 Input 32 Bit Muxes := 6
5 Input 32 Bit Muxes := 2
3 Input 31 Bit Muxes := 1
48 Input 24 Bit Muxes := 1
2 Input 12 Bit Muxes := 4
8 Input 12 Bit Muxes := 1
4 Input 8 Bit Muxes := 1
48 Input 8 Bit Muxes := 2
2 Input 8 Bit Muxes := 4
24 Input 7 Bit Muxes := 1
2 Input 7 Bit Muxes := 2
3 Input 6 Bit Muxes := 1
2 Input 5 Bit Muxes := 5
18 Input 5 Bit Muxes := 3
3 Input 4 Bit Muxes := 1
2 Input 4 Bit Muxes := 5
8 Input 4 Bit Muxes := 1
2 Input 3 Bit Muxes := 27
8 Input 3 Bit Muxes := 2
5 Input 3 Bit Muxes := 5
21 Input 3 Bit Muxes := 1
3 Input 3 Bit Muxes := 1
8 Input 2 Bit Muxes := 4
2 Input 2 Bit Muxes := 49
4 Input 2 Bit Muxes := 5
13 Input 2 Bit Muxes := 1
3 Input 2 Bit Muxes := 2
48 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 501
7 Input 1 Bit Muxes := 8
4 Input 1 Bit Muxes := 31
6 Input 1 Bit Muxes := 10
3 Input 1 Bit Muxes := 43
18 Input 1 Bit Muxes := 3
8 Input 1 Bit Muxes := 27
5 Input 1 Bit Muxes := 16
13 Input 1 Bit Muxes := 2
23 Input 1 Bit Muxes := 1
48 Input 1 Bit Muxes := 22
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 240 (col length:80)
BRAMs: 270 (col length: RAMB18 80 RAMB36 40)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[0]' (FDCPE) to 'CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[1]' (FDCPE) to 'CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[2]' (FDCPE) to 'CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[4]' (FDCPE) to 'CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[5]' (FDCPE) to 'CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[6]' (FDCPE) to 'CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[8]' (FDCPE) to 'CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[9]' (FDCPE) to 'CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[10]' (FDCPE) to 'CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[11]' (FDCPE) to 'CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[12]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[13]' (FDCPE) to 'CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[14]' (FDCPE) to 'CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[15]' (FDCPE) to 'CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[16]' (FDCPE) to 'CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[17]' (FDCPE) to 'CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[18]' (FDCPE) to 'CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[19]' (FDCPE) to 'CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[20]' (FDCPE) to 'CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[21]' (FDCPE) to 'CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[22]' (FDCPE) to 'CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[23]' (FDCPE) to 'CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[24]' (FDCPE) to 'CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[25]' (FDCPE) to 'CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[26]' (FDCPE) to 'CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[27]' (FDCPE) to 'CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[28]' (FDCPE) to 'CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[29]' (FDCPE) to 'CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[30]' (FDCPE) to 'CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\CSR_updating_logic[1].TMR_CMP_MSTATUS /\tmr_reg_o_int_data_A_reg[31] )
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[2].TMR_CMP_MIP/tmr_reg_o_int_data_A_reg[7]' (FDCE) to 'CSR_updating_logic[2].TMR_CMP_MIP/tmr_reg_o_int_data_A_reg[11]'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\CSR_updating_logic[2].TMR_CMP_MIP /\tmr_reg_o_int_data_A_reg[11] )
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[0]' (FDCPE) to 'CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[1]' (FDCPE) to 'CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[2]' (FDCPE) to 'CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[4]' (FDCPE) to 'CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[5]' (FDCPE) to 'CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[6]' (FDCPE) to 'CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[8]' (FDCPE) to 'CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[9]' (FDCPE) to 'CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[10]' (FDCPE) to 'CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[11]' (FDCPE) to 'CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[12]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[13]' (FDCPE) to 'CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[14]' (FDCPE) to 'CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[15]' (FDCPE) to 'CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[16]' (FDCPE) to 'CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[17]' (FDCPE) to 'CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[18]' (FDCPE) to 'CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[19]' (FDCPE) to 'CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[20]' (FDCPE) to 'CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[21]' (FDCPE) to 'CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[22]' (FDCPE) to 'CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[23]' (FDCPE) to 'CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[24]' (FDCPE) to 'CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[25]' (FDCPE) to 'CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[26]' (FDCPE) to 'CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[27]' (FDCPE) to 'CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[28]' (FDCPE) to 'CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[29]' (FDCPE) to 'CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[30]' (FDCPE) to 'CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\CSR_updating_logic[2].TMR_CMP_MSTATUS /\tmr_reg_o_int_data_A_reg[31] )
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[0]' (FDCPE) to 'CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[1]' (FDCPE) to 'CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[2]' (FDCPE) to 'CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[4]' (FDCPE) to 'CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[5]' (FDCPE) to 'CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[6]' (FDCPE) to 'CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[8]' (FDCPE) to 'CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[9]' (FDCPE) to 'CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[10]' (FDCPE) to 'CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[11]' (FDCPE) to 'CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[12]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[13]' (FDCPE) to 'CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[14]' (FDCPE) to 'CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[15]' (FDCPE) to 'CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[16]' (FDCPE) to 'CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[17]' (FDCPE) to 'CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[18]' (FDCPE) to 'CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[19]' (FDCPE) to 'CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[20]' (FDCPE) to 'CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[21]' (FDCPE) to 'CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[22]' (FDCPE) to 'CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[23]' (FDCPE) to 'CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[24]' (FDCPE) to 'CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[25]' (FDCPE) to 'CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[26]' (FDCPE) to 'CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[27]' (FDCPE) to 'CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[28]' (FDCPE) to 'CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[29]' (FDCPE) to 'CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[30]' (FDCPE) to 'CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[31]'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\CSR_updating_logic[0].TMR_CMP_MSTATUS /\tmr_reg_o_int_data_A_reg[31] )
INFO: [Synth 8-3886] merging instance 'CSR_updating_logic[1].TMR_CMP_MIP/tmr_reg_o_int_data_A_reg[7]' (FDCE) to 'CSR_updating_logic[1].TMR_CMP_MIP/tmr_reg_o_int_data_A_reg[11]'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\CSR_updating_logic[1].TMR_CMP_MIP /\tmr_reg_o_int_data_A_reg[11] )
INFO: [Synth 8-5546] ROM "decoded_instruction_IE_wire" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "decoded_instruction_IE_wire" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "decoded_instruction_IE_wire" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "decoded_instruction_IE_wire" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "decoded_instruction_IE_wire" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-3886] merging instance 'state_IE_reg[3]' (FDC) to 'state_IE_reg[0]'
INFO: [Synth 8-3886] merging instance 'state_IE_reg[6]' (FDC) to 'state_IE_reg[0]'
INFO: [Synth 8-3886] merging instance 'state_IE_reg[4]' (FDC) to 'state_IE_reg[1]'
INFO: [Synth 8-3886] merging instance 'state_IE_reg[7]' (FDC) to 'state_IE_reg[1]'
INFO: [Synth 8-3886] merging instance 'state_IE_reg[5]' (FDC) to 'state_IE_reg[2]'
INFO: [Synth 8-3886] merging instance 'state_IE_reg[8]' (FDC) to 'state_IE_reg[2]'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\fsm_IE_comb.PC_offset_wires_reg[0][0] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\fsm_IE_comb.PC_offset_wires_reg[1][0] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\fsm_IE_comb.PC_offset_wires_reg[2][0] )
INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-3886] merging instance 'DBG/debug_rdata_o_regi_85' (FDCE) to 'DBG/debug_rdata_o_regi_84'
INFO: [Synth 8-3886] merging instance 'DBG/debug_rdata_o_regi_84' (FDCE) to 'DBG/debug_rdata_o_regi_83'
INFO: [Synth 8-3886] merging instance 'DBG/debug_rdata_o_regi_83' (FDCE) to 'DBG/debug_rdata_o_regi_82'
INFO: [Synth 8-3886] merging instance 'DBG/debug_rdata_o_regi_82' (FDCE) to 'DBG/debug_rdata_o_regi_81'
INFO: [Synth 8-3886] merging instance 'DBG/debug_rdata_o_regi_81' (FDCE) to 'DBG/debug_rdata_o_regi_80'
INFO: [Synth 8-3886] merging instance 'DBG/debug_rdata_o_regi_80' (FDCE) to 'DBG/debug_rdata_o_regi_79'
INFO: [Synth 8-3886] merging instance 'DBG/debug_rdata_o_regi_79' (FDCE) to 'DBG/debug_rdata_o_regi_78'
INFO: [Synth 8-3886] merging instance 'DBG/debug_rdata_o_regi_78' (FDCE) to 'DBG/debug_rdata_o_regi_77'
INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:49 ; elapsed = 00:01:18 . Memory (MB): peak = 2359.375 ; gain = 730.312 ; free physical = 225 ; free virtual = 22212
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
ROM: Preliminary Mapping Report
+------------+---------------------+---------------+----------------+
|Module Name | RTL Object | Depth x Width | Implemented As |
+------------+---------------------+---------------+----------------+
|Interpreter | memory_mux_selector | 256x1 | LUT |
|Interpreter | memory_mux_selector | 256x1 | LUT |
+------------+---------------------+---------------+----------------+
Distributed RAM: Preliminary Mapping Report (see note below)
+----------------+------------------------------------------+-----------+----------------------+------------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+----------------+------------------------------------------+-----------+----------------------+------------------+
|processorci_top | u_Controller/Uart/tx_fifo/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
|processorci_top | u_Controller/Uart/rx_fifo/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
|processorci_top | u_Controller/Core_Memory/memory_reg | Implied | 2 K x 32 | RAM256X1S x 256 |
|processorci_top | u_Controller/Core_Data_Memory/memory_reg | Implied | 1 K x 32 | RAM256X1S x 128 |
+----------------+------------------------------------------+-----------+----------------------+------------------+
Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:55 ; elapsed = 00:01:23 . Memory (MB): peak = 2359.375 ; gain = 730.312 ; free physical = 210 ; free virtual = 22210
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-3332] Sequential element (debug_rdata_o_regi_53) is unused and will be removed from module Debug_UNIT.
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:01:01 ; elapsed = 00:01:30 . Memory (MB): peak = 2359.375 ; gain = 730.312 ; free physical = 210 ; free virtual = 22208
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Distributed RAM: Final Mapping Report
+----------------+------------------------------------------+-----------+----------------------+------------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+----------------+------------------------------------------+-----------+----------------------+------------------+
|processorci_top | u_Controller/Uart/tx_fifo/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
|processorci_top | u_Controller/Uart/rx_fifo/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
|processorci_top | u_Controller/Core_Memory/memory_reg | Implied | 2 K x 32 | RAM256X1S x 256 |
|processorci_top | u_Controller/Core_Data_Memory/memory_reg | Implied | 1 K x 32 | RAM256X1S x 128 |
+----------------+------------------------------------------+-----------+----------------------+------------------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:01:05 ; elapsed = 00:01:41 . Memory (MB): peak = 2359.375 ; gain = 730.312 ; free physical = 228 ; free virtual = 22126
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:01:11 ; elapsed = 00:01:46 . Memory (MB): peak = 2359.375 ; gain = 730.312 ; free physical = 213 ; free virtual = 22123
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:01:11 ; elapsed = 00:01:47 . Memory (MB): peak = 2359.375 ; gain = 730.312 ; free physical = 213 ; free virtual = 22123
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:12 ; elapsed = 00:01:48 . Memory (MB): peak = 2359.375 ; gain = 730.312 ; free physical = 212 ; free virtual = 22123
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:01:13 ; elapsed = 00:01:48 . Memory (MB): peak = 2359.375 ; gain = 730.312 ; free physical = 212 ; free virtual = 22123
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:01:13 ; elapsed = 00:01:49 . Memory (MB): peak = 2359.375 ; gain = 730.312 ; free physical = 212 ; free virtual = 22123
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:01:13 ; elapsed = 00:01:49 . Memory (MB): peak = 2359.375 ; gain = 730.312 ; free physical = 212 ; free virtual = 22123
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+----------+------+
| |Cell |Count |
+------+----------+------+
|1 |BUFG | 9|
|2 |CARRY4 | 413|
|3 |LUT1 | 235|
|4 |LUT2 | 896|
|5 |LUT3 | 1455|
|6 |LUT4 | 2016|
|7 |LUT5 | 1696|
|8 |LUT6 | 5663|
|9 |MUXF7 | 267|
|10 |RAM256X1S | 384|
|11 |RAM32M | 2|
|12 |RAM32X1D | 4|
|13 |FDCE | 4574|
|14 |FDPE | 10|
|15 |FDRE | 852|
|16 |FDSE | 4|
|17 |LD | 268|
|18 |LDC | 39|
|19 |LDP | 3|
|20 |IBUF | 2|
|21 |OBUF | 2|
|22 |OBUFT | 1|
+------+----------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:01:13 ; elapsed = 00:01:49 . Memory (MB): peak = 2359.375 ; gain = 730.312 ; free physical = 212 ; free virtual = 22123
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 117 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:01:09 ; elapsed = 00:01:44 . Memory (MB): peak = 2359.375 ; gain = 589.527 ; free physical = 5873 ; free virtual = 27784
Synthesis Optimization Complete : Time (s): cpu = 00:01:16 ; elapsed = 00:01:49 . Memory (MB): peak = 2359.375 ; gain = 730.312 ; free physical = 5876 ; free virtual = 27780
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.18 ; elapsed = 00:00:00.17 . Memory (MB): peak = 2359.375 ; gain = 0.000 ; free physical = 5871 ; free virtual = 27775
INFO: [Netlist 29-17] Analyzing 1380 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]
WARNING: [Vivado 12-507] No nets matched 'sck_IBUF'. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
Finished Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2447.383 ; gain = 0.000 ; free physical = 5877 ; free virtual = 27781
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 700 instances were transformed.
LD => LDCE: 268 instances
LDC => LDCE: 39 instances
LDP => LDPE: 3 instances
RAM256X1S => RAM256X1S (MUXF7(x2), MUXF8, RAMS64E(x4)): 384 instances
RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 2 instances
RAM32X1D => RAM32X1D (RAMD32(x2)): 4 instances
Synth Design complete | Checksum: f2b95c5a
INFO: [Common 17-83] Releasing license: Synthesis
311 Infos, 144 Warnings, 2 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:01:25 ; elapsed = 00:01:58 . Memory (MB): peak = 2447.418 ; gain = 1126.426 ; free physical = 5877 ; free virtual = 27781
INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 7479.742; main = 1833.789; forked = 6013.623
INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 12322.383; main = 2447.387; forked = 9987.051
# opt_design
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command opt_design
Starting DRC Task
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.55 . Memory (MB): peak = 2511.414 ; gain = 63.996 ; free physical = 5877 ; free virtual = 27781
Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 2451592af
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2591.227 ; gain = 79.812 ; free physical = 5847 ; free virtual = 27751
Starting Logic Optimization Task
Phase 1 Initialization
Phase 1.1 Core Generation And Design Setup
Phase 1.1 Core Generation And Design Setup | Checksum: 2451592af
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2841.102 ; gain = 0.000 ; free physical = 5565 ; free virtual = 27469
Phase 1.2 Setup Constraints And Sort Netlist
Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 2451592af
Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2841.102 ; gain = 0.000 ; free physical = 5565 ; free virtual = 27469
Phase 1 Initialization | Checksum: 2451592af
Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2841.102 ; gain = 0.000 ; free physical = 5565 ; free virtual = 27469
Phase 2 Timer Update And Timing Data Collection
Phase 2.1 Timer Update
Phase 2.1 Timer Update | Checksum: 2451592af
Time (s): cpu = 00:00:00.89 ; elapsed = 00:00:00.25 . Memory (MB): peak = 2841.102 ; gain = 0.000 ; free physical = 5565 ; free virtual = 27469
Phase 2.2 Timing Data Collection
Phase 2.2 Timing Data Collection | Checksum: 2451592af
Time (s): cpu = 00:00:00.93 ; elapsed = 00:00:00.28 . Memory (MB): peak = 2841.102 ; gain = 0.000 ; free physical = 5565 ; free virtual = 27469
Phase 2 Timer Update And Timing Data Collection | Checksum: 2451592af
Time (s): cpu = 00:00:00.93 ; elapsed = 00:00:00.28 . Memory (MB): peak = 2841.102 ; gain = 0.000 ; free physical = 5565 ; free virtual = 27469
Phase 3 Retarget
INFO: [Opt 31-1566] Pulled 5 inverters resulting in an inversion of 165 pins
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 3 Retarget | Checksum: 27b85c7e5
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.54 . Memory (MB): peak = 2841.102 ; gain = 0.000 ; free physical = 5565 ; free virtual = 27469
Retarget | Checksum: 27b85c7e5
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 6 cells
Phase 4 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 4 Constant propagation | Checksum: 23430c5ea
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.85 . Memory (MB): peak = 2841.102 ; gain = 0.000 ; free physical = 5565 ; free virtual = 27469
Constant propagation | Checksum: 23430c5ea
INFO: [Opt 31-389] Phase Constant propagation created 323 cells and removed 408 cells
Phase 5 Sweep
Phase 5 Sweep | Checksum: 2176a4637
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2841.102 ; gain = 0.000 ; free physical = 5565 ; free virtual = 27469
Sweep | Checksum: 2176a4637
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 65 cells
Phase 6 BUFG optimization
INFO: [Opt 31-194] Inserted BUFG u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_IE/E[0]_BUFG_inst to drive 31 load(s) on clock net u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_IE/E_BUFG[0]
INFO: [Opt 31-194] Inserted BUFG u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_IE/tmr_sreg_o_int_data_A_reg_8[0]_BUFG_inst to drive 31 load(s) on clock net u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_IE/tmr_sreg_o_int_data_A_reg_8_BUFG[0]
INFO: [Opt 31-194] Inserted BUFG u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_IE/tmr_sreg_o_int_data_A_reg_9[0]_BUFG_inst to drive 31 load(s) on clock net u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_IE/tmr_sreg_o_int_data_A_reg_9_BUFG[0]
INFO: [Opt 31-193] Inserted 3 BUFG(s) on clock nets
Phase 6 BUFG optimization | Checksum: 1e72612c0
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2873.117 ; gain = 32.016 ; free physical = 5565 ; free virtual = 27469
BUFG optimization | Checksum: 1e72612c0
INFO: [Opt 31-662] Phase BUFG optimization created 3 cells of which 3 are BUFGs and removed 0 cells.
Phase 7 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 7 Shift Register Optimization | Checksum: 1e72612c0
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2873.117 ; gain = 32.016 ; free physical = 5565 ; free virtual = 27469
Shift Register Optimization | Checksum: 1e72612c0
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 8 Post Processing Netlist
Phase 8 Post Processing Netlist | Checksum: 1e72612c0
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2873.117 ; gain = 32.016 ; free physical = 5565 ; free virtual = 27469
Post Processing Netlist | Checksum: 1e72612c0
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Phase 9 Finalization
Phase 9.1 Finalizing Design Cores and Updating Shapes
Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 15551e447
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2873.117 ; gain = 32.016 ; free physical = 5565 ; free virtual = 27469
Phase 9.2 Verifying Netlist Connectivity
Starting Connectivity Check Task
Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2873.117 ; gain = 0.000 ; free physical = 5564 ; free virtual = 27468
Phase 9.2 Verifying Netlist Connectivity | Checksum: 15551e447
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2873.117 ; gain = 32.016 ; free physical = 5564 ; free virtual = 27468
Phase 9 Finalization | Checksum: 15551e447
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2873.117 ; gain = 32.016 ; free physical = 5563 ; free virtual = 27467
Opt_design Change Summary
=========================
-------------------------------------------------------------------------------------------------------------------------
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
-------------------------------------------------------------------------------------------------------------------------
| Retarget | 0 | 6 | 0 |
| Constant propagation | 323 | 408 | 0 |
| Sweep | 0 | 65 | 0 |
| BUFG optimization | 3 | 0 | 0 |
| Shift Register Optimization | 0 | 0 | 0 |
| Post Processing Netlist | 0 | 0 | 0 |
-------------------------------------------------------------------------------------------------------------------------
Ending Logic Optimization Task | Checksum: 15551e447
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2873.117 ; gain = 32.016 ; free physical = 5563 ; free virtual = 27467
INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
Done building netlist checker database: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2873.117 ; gain = 0.000 ; free physical = 5561 ; free virtual = 27465
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 15551e447
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2873.117 ; gain = 0.000 ; free physical = 5556 ; free virtual = 27460
Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 15551e447
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2873.117 ; gain = 0.000 ; free physical = 5556 ; free virtual = 27460
Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2873.117 ; gain = 0.000 ; free physical = 5555 ; free virtual = 27459
Ending Netlist Obfuscation Task | Checksum: 15551e447
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2873.117 ; gain = 0.000 ; free physical = 5555 ; free virtual = 27459
INFO: [Common 17-83] Releasing license: Implementation
23 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 2873.117 ; gain = 425.699 ; free physical = 5554 ; free virtual = 27458
# place_design
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-83] Releasing license: Implementation
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs
Starting Placer Task
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2905.133 ; gain = 0.000 ; free physical = 5559 ; free virtual = 27463
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 12ac6d467
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2905.133 ; gain = 0.000 ; free physical = 5559 ; free virtual = 27463
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2905.133 ; gain = 0.000 ; free physical = 5558 ; free virtual = 27462
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: d03ec8f4
Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 2905.133 ; gain = 0.000 ; free physical = 5551 ; free virtual = 27455
Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 1845c36ba
Time (s): cpu = 00:00:16 ; elapsed = 00:00:07 . Memory (MB): peak = 2912.160 ; gain = 7.027 ; free physical = 5538 ; free virtual = 27442
Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 1845c36ba
Time (s): cpu = 00:00:16 ; elapsed = 00:00:07 . Memory (MB): peak = 2912.160 ; gain = 7.027 ; free physical = 5538 ; free virtual = 27442
Phase 1 Placer Initialization | Checksum: 1845c36ba
Time (s): cpu = 00:00:16 ; elapsed = 00:00:07 . Memory (MB): peak = 2912.160 ; gain = 7.027 ; free physical = 5539 ; free virtual = 27443
Phase 2 Global Placement
Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 1bc3f48d6
Time (s): cpu = 00:00:17 ; elapsed = 00:00:07 . Memory (MB): peak = 2912.160 ; gain = 7.027 ; free physical = 5538 ; free virtual = 27442
Phase 2.2 Update Timing before SLR Path Opt
Phase 2.2 Update Timing before SLR Path Opt | Checksum: 19a078f94
Time (s): cpu = 00:00:17 ; elapsed = 00:00:07 . Memory (MB): peak = 2912.160 ; gain = 7.027 ; free physical = 5538 ; free virtual = 27442
Phase 2.3 Post-Processing in Floorplanning
Phase 2.3 Post-Processing in Floorplanning | Checksum: 19a078f94
Time (s): cpu = 00:00:17 ; elapsed = 00:00:07 . Memory (MB): peak = 2912.160 ; gain = 7.027 ; free physical = 5538 ; free virtual = 27442
Phase 2.4 Global Placement Core
Phase 2.4.1 UpdateTiming Before Physical Synthesis
Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 1104801ac
Time (s): cpu = 00:00:30 ; elapsed = 00:00:11 . Memory (MB): peak = 2912.160 ; gain = 7.027 ; free physical = 5547 ; free virtual = 27451
Phase 2.4.2 Physical Synthesis In Placer
INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 590 LUT instances to create LUTNM shape
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
INFO: [Physopt 32-1138] End 1 Pass. Optimized 269 nets or LUTs. Breaked 0 LUT, combined 269 existing LUTs and moved 0 existing LUT
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed.
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2912.160 ; gain = 0.000 ; free physical = 5551 ; free virtual = 27455
Summary of Physical Synthesis Optimizations
============================================
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| LUT Combining | 0 | 269 | 269 | 0 | 1 | 00:00:01 |
| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Total | 0 | 269 | 269 | 0 | 4 | 00:00:01 |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
Phase 2.4.2 Physical Synthesis In Placer | Checksum: a5e422cc
Time (s): cpu = 00:00:32 ; elapsed = 00:00:13 . Memory (MB): peak = 2912.160 ; gain = 7.027 ; free physical = 5551 ; free virtual = 27455
Phase 2.4 Global Placement Core | Checksum: 16f2ca7f7
Time (s): cpu = 00:00:35 ; elapsed = 00:00:13 . Memory (MB): peak = 2912.160 ; gain = 7.027 ; free physical = 5551 ; free virtual = 27455
Phase 2 Global Placement | Checksum: 16f2ca7f7
Time (s): cpu = 00:00:35 ; elapsed = 00:00:13 . Memory (MB): peak = 2912.160 ; gain = 7.027 ; free physical = 5551 ; free virtual = 27455
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 12c6aef37
Time (s): cpu = 00:00:35 ; elapsed = 00:00:13 . Memory (MB): peak = 2912.160 ; gain = 7.027 ; free physical = 5546 ; free virtual = 27450
Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1d38e5dec
Time (s): cpu = 00:00:35 ; elapsed = 00:00:14 . Memory (MB): peak = 2912.160 ; gain = 7.027 ; free physical = 5543 ; free virtual = 27447
Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 1b22c30ee
Time (s): cpu = 00:00:36 ; elapsed = 00:00:14 . Memory (MB): peak = 2912.160 ; gain = 7.027 ; free physical = 5556 ; free virtual = 27460
Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 1780620f9
Time (s): cpu = 00:00:36 ; elapsed = 00:00:14 . Memory (MB): peak = 2912.160 ; gain = 7.027 ; free physical = 5556 ; free virtual = 27460
Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: 1af2aaca9
Time (s): cpu = 00:00:41 ; elapsed = 00:00:19 . Memory (MB): peak = 2912.160 ; gain = 7.027 ; free physical = 5555 ; free virtual = 27459
Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: 19e67c954
Time (s): cpu = 00:00:42 ; elapsed = 00:00:20 . Memory (MB): peak = 2912.160 ; gain = 7.027 ; free physical = 5559 ; free virtual = 27463
Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: 158adf949
Time (s): cpu = 00:00:42 ; elapsed = 00:00:20 . Memory (MB): peak = 2912.160 ; gain = 7.027 ; free physical = 5559 ; free virtual = 27463
Phase 3 Detail Placement | Checksum: 158adf949
Time (s): cpu = 00:00:42 ; elapsed = 00:00:20 . Memory (MB): peak = 2912.160 ; gain = 7.027 ; free physical = 5559 ; free virtual = 27463
Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 1c92b13b1
Phase 4.1.1.1 BUFG Insertion
Starting Physical Synthesis Task
Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=8.875 | TNS=0.000 |
Phase 1 Physical Synthesis Initialization | Checksum: 1988f51e8
Time (s): cpu = 00:00:00.9 ; elapsed = 00:00:00.33 . Memory (MB): peak = 2912.160 ; gain = 0.000 ; free physical = 5551 ; free virtual = 27455
INFO: [Place 46-33] Processed net u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_WB/core_reset_reg[0], BUFG insertion was skipped due to placement/routing conflicts.
INFO: [Place 46-56] BUFG insertion identified 1 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 1, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
Ending Physical Synthesis Task | Checksum: 1988f51e8
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.65 . Memory (MB): peak = 2912.160 ; gain = 0.000 ; free physical = 5551 ; free virtual = 27455
Phase 4.1.1.1 BUFG Insertion | Checksum: 1c92b13b1
Time (s): cpu = 00:00:56 ; elapsed = 00:00:24 . Memory (MB): peak = 2912.160 ; gain = 7.027 ; free physical = 5551 ; free virtual = 27455
Phase 4.1.1.2 Post Placement Timing Optimization
INFO: [Place 30-746] Post Placement Timing Summary WNS=8.875. For the most accurate timing information please run report_timing.
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1d5654ddb
Time (s): cpu = 00:00:56 ; elapsed = 00:00:24 . Memory (MB): peak = 2912.160 ; gain = 7.027 ; free physical = 5551 ; free virtual = 27455
Time (s): cpu = 00:00:56 ; elapsed = 00:00:24 . Memory (MB): peak = 2912.160 ; gain = 7.027 ; free physical = 5551 ; free virtual = 27455
Phase 4.1 Post Commit Optimization | Checksum: 1d5654ddb
Time (s): cpu = 00:00:56 ; elapsed = 00:00:24 . Memory (MB): peak = 2912.160 ; gain = 7.027 ; free physical = 5551 ; free virtual = 27455
Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 1d5654ddb
Time (s): cpu = 00:00:56 ; elapsed = 00:00:24 . Memory (MB): peak = 2912.160 ; gain = 7.027 ; free physical = 5551 ; free virtual = 27455
Phase 4.3 Placer Reporting
Phase 4.3.1 Print Estimated Congestion
INFO: [Place 30-612] Post-Placement Estimated Congestion
____________________________________________________
| | Global Congestion | Short Congestion |
| Direction | Region Size | Region Size |
|___________|___________________|___________________|
| North| 1x1| 2x2|
|___________|___________________|___________________|
| South| 1x1| 1x1|
|___________|___________________|___________________|
| East| 1x1| 1x1|
|___________|___________________|___________________|
| West| 1x1| 2x2|
|___________|___________________|___________________|
Phase 4.3.1 Print Estimated Congestion | Checksum: 1d5654ddb
Time (s): cpu = 00:00:56 ; elapsed = 00:00:24 . Memory (MB): peak = 2912.160 ; gain = 7.027 ; free physical = 5551 ; free virtual = 27455
Phase 4.3 Placer Reporting | Checksum: 1d5654ddb
Time (s): cpu = 00:00:57 ; elapsed = 00:00:24 . Memory (MB): peak = 2912.160 ; gain = 7.027 ; free physical = 5551 ; free virtual = 27455
Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2912.160 ; gain = 0.000 ; free physical = 5551 ; free virtual = 27455
Time (s): cpu = 00:00:57 ; elapsed = 00:00:24 . Memory (MB): peak = 2912.160 ; gain = 7.027 ; free physical = 5551 ; free virtual = 27455
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1cd7f4843
Time (s): cpu = 00:00:57 ; elapsed = 00:00:24 . Memory (MB): peak = 2912.160 ; gain = 7.027 ; free physical = 5551 ; free virtual = 27455
Ending Placer Task | Checksum: 1661e3c70
Time (s): cpu = 00:00:57 ; elapsed = 00:00:24 . Memory (MB): peak = 2912.160 ; gain = 7.027 ; free physical = 5543 ; free virtual = 27447
30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:00:59 ; elapsed = 00:00:25 . Memory (MB): peak = 2912.160 ; gain = 39.043 ; free physical = 5543 ; free virtual = 27447
# report_utilization -hierarchical -file digilent_arty_a7_utilization_hierarchical_place.rpt
# report_utilization -file digilent_arty_a7_utilization_place.rpt
# report_io -file digilent_arty_a7_io.rpt
report_io: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2912.160 ; gain = 0.000 ; free physical = 5542 ; free virtual = 27446
# report_control_sets -verbose -file digilent_arty_a7_control_sets.rpt
report_control_sets: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2912.160 ; gain = 0.000 ; free physical = 5542 ; free virtual = 27447
# report_clock_utilization -file digilent_arty_a7_clock_utilization.rpt
# route_design
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
Phase 1 Build RT Design
Checksum: PlaceDB: 7a214650 ConstDB: 0 ShapeSum: ebfcf620 RouteDB: 0
Post Restoration Checksum: NetGraph: a576daca | NumContArr: 14aa696a | Constraints: c2a8fa9d | Timing: c2a8fa9d
Phase 1 Build RT Design | Checksum: 23f73396e
Time (s): cpu = 00:00:43 ; elapsed = 00:00:27 . Memory (MB): peak = 2968.188 ; gain = 0.000 ; free physical = 5525 ; free virtual = 27430
Phase 2 Router Initialization
Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 23f73396e
Time (s): cpu = 00:00:43 ; elapsed = 00:00:27 . Memory (MB): peak = 2968.188 ; gain = 0.000 ; free physical = 5525 ; free virtual = 27430
Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 23f73396e
Time (s): cpu = 00:00:43 ; elapsed = 00:00:27 . Memory (MB): peak = 2968.188 ; gain = 0.000 ; free physical = 5525 ; free virtual = 27430
Number of Nodes with overlaps = 0
Phase 2.3 Update Timing
Phase 2.3 Update Timing | Checksum: 2c6477977
Time (s): cpu = 00:01:00 ; elapsed = 00:00:33 . Memory (MB): peak = 2968.188 ; gain = 0.000 ; free physical = 5463 ; free virtual = 27368
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.797 | TNS=0.000 | WHS=0.008 | THS=0.000 |
Router Utilization Summary
Global Vertical Routing Utilization = 0.350307 %
Global Horizontal Routing Utilization = 0.38825 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 15125
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 14764
Number of Partially Routed Nets = 361
Number of Node Overlaps = 1948
Phase 2 Router Initialization | Checksum: 323657ad3
Time (s): cpu = 00:01:06 ; elapsed = 00:00:34 . Memory (MB): peak = 2968.188 ; gain = 0.000 ; free physical = 5463 ; free virtual = 27368
Phase 3 Initial Routing
Phase 3.1 Global Routing
Phase 3.1 Global Routing | Checksum: 323657ad3
Time (s): cpu = 00:01:06 ; elapsed = 00:00:34 . Memory (MB): peak = 2968.188 ; gain = 0.000 ; free physical = 5463 ; free virtual = 27368
Phase 3.2 Initial Net Routing
Phase 3.2 Initial Net Routing | Checksum: 1b848736e
Time (s): cpu = 00:01:12 ; elapsed = 00:00:35 . Memory (MB): peak = 2968.188 ; gain = 0.000 ; free physical = 5456 ; free virtual = 27360
Phase 3 Initial Routing | Checksum: 1b848736e
Time (s): cpu = 00:01:12 ; elapsed = 00:00:35 . Memory (MB): peak = 2968.188 ; gain = 0.000 ; free physical = 5456 ; free virtual = 27360
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
Number of Nodes with overlaps = 1570
Number of Nodes with overlaps = 4
Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.401 | TNS=0.000 | WHS=N/A | THS=N/A |
Phase 4.1 Global Iteration 0 | Checksum: 18dcd8a96
Time (s): cpu = 00:01:26 ; elapsed = 00:00:41 . Memory (MB): peak = 2968.188 ; gain = 0.000 ; free physical = 5450 ; free virtual = 27354
Phase 4 Rip-up And Reroute | Checksum: 18dcd8a96
Time (s): cpu = 00:01:26 ; elapsed = 00:00:41 . Memory (MB): peak = 2968.188 ; gain = 0.000 ; free physical = 5449 ; free virtual = 27354
Phase 5 Delay and Skew Optimization
Phase 5.1 Delay CleanUp
Phase 5.1 Delay CleanUp | Checksum: 18dcd8a96
Time (s): cpu = 00:01:26 ; elapsed = 00:00:41 . Memory (MB): peak = 2968.188 ; gain = 0.000 ; free physical = 5463 ; free virtual = 27368
Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 18dcd8a96
Time (s): cpu = 00:01:26 ; elapsed = 00:00:41 . Memory (MB): peak = 2968.188 ; gain = 0.000 ; free physical = 5463 ; free virtual = 27368
Phase 5 Delay and Skew Optimization | Checksum: 18dcd8a96
Time (s): cpu = 00:01:26 ; elapsed = 00:00:41 . Memory (MB): peak = 2968.188 ; gain = 0.000 ; free physical = 5463 ; free virtual = 27368
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 1b99f0f76
Time (s): cpu = 00:01:28 ; elapsed = 00:00:41 . Memory (MB): peak = 2968.188 ; gain = 0.000 ; free physical = 5463 ; free virtual = 27367
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.497 | TNS=0.000 | WHS=0.431 | THS=0.000 |
Phase 6.1 Hold Fix Iter | Checksum: 1b99f0f76
Time (s): cpu = 00:01:28 ; elapsed = 00:00:41 . Memory (MB): peak = 2968.188 ; gain = 0.000 ; free physical = 5463 ; free virtual = 27367
Phase 6 Post Hold Fix | Checksum: 1b99f0f76
Time (s): cpu = 00:01:28 ; elapsed = 00:00:41 . Memory (MB): peak = 2968.188 ; gain = 0.000 ; free physical = 5463 ; free virtual = 27367
Phase 7 Route finalize
Router Utilization Summary
Global Vertical Routing Utilization = 3.89372 %
Global Horizontal Routing Utilization = 4.83113 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 0
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 0
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
Phase 7 Route finalize | Checksum: 1b99f0f76
Time (s): cpu = 00:01:28 ; elapsed = 00:00:42 . Memory (MB): peak = 2968.188 ; gain = 0.000 ; free physical = 5463 ; free virtual = 27367
Phase 8 Verifying routed nets
Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 1b99f0f76
Time (s): cpu = 00:01:28 ; elapsed = 00:00:42 . Memory (MB): peak = 2968.188 ; gain = 0.000 ; free physical = 5463 ; free virtual = 27367
Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 255b66541
Time (s): cpu = 00:01:31 ; elapsed = 00:00:43 . Memory (MB): peak = 2968.188 ; gain = 0.000 ; free physical = 5463 ; free virtual = 27367
Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=8.497 | TNS=0.000 | WHS=0.431 | THS=0.000 |
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 10 Post Router Timing | Checksum: 255b66541
Time (s): cpu = 00:01:32 ; elapsed = 00:00:43 . Memory (MB): peak = 2968.188 ; gain = 0.000 ; free physical = 5462 ; free virtual = 27366
INFO: [Route 35-16] Router Completed Successfully
Phase 11 Post-Route Event Processing
Phase 11 Post-Route Event Processing | Checksum: 1825c5649
Time (s): cpu = 00:01:32 ; elapsed = 00:00:44 . Memory (MB): peak = 2968.188 ; gain = 0.000 ; free physical = 5458 ; free virtual = 27363
Ending Routing Task | Checksum: 1825c5649
Time (s): cpu = 00:01:33 ; elapsed = 00:00:44 . Memory (MB): peak = 2968.188 ; gain = 0.000 ; free physical = 5455 ; free virtual = 27360
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
12 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:01:36 ; elapsed = 00:00:46 . Memory (MB): peak = 2968.188 ; gain = 0.000 ; free physical = 5452 ; free virtual = 27357
# report_timing_summary -no_header -no_detailed_paths
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------
Enable Multi Corner Analysis : Yes
Enable Pessimism Removal : Yes
Pessimism Removal Resolution : Nearest Common Node
Enable Input Delay Default Clock : No
Enable Preset / Clear Arcs : No
Disable Flight Delays : No
Ignore I/O Paths : No
Timing Early Launch at Borrowing Latches : No
Borrow Time for Max Delay Exceptions : Yes
Merge Timing Exceptions : Yes
Inter-SLR Compensation : Conservative
Corner Analyze Analyze
Name Max Paths Min Paths
------ --------- ---------
Slow Yes Yes
Fast Yes Yes
------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------
No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations.
check_timing report
Table of Contents
-----------------
1. checking no_clock (172212)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (31431)
5. checking no_input_delay (1)
6. checking no_output_delay (1)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)
1. checking no_clock (172212)
-----------------------------
There are 6967 register/latch pins with no clock driven by root clock pin: clk_o_reg/Q (HIGH)
There are 4745 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[0]/Q (HIGH)
There are 4745 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[10]/Q (HIGH)
There are 4745 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[11]/Q (HIGH)
There are 4745 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[12]/Q (HIGH)
There are 4745 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[13]/Q (HIGH)
There are 4745 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[14]/Q (HIGH)
There are 4745 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[15]/Q (HIGH)
There are 4745 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[16]/Q (HIGH)
There are 4745 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[17]/Q (HIGH)
There are 4745 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[18]/Q (HIGH)
There are 4745 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[19]/Q (HIGH)
There are 4745 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[1]/Q (HIGH)
There are 4745 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[20]/Q (HIGH)
There are 4745 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[21]/Q (HIGH)
There are 4745 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[22]/Q (HIGH)
There are 4745 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[23]/Q (HIGH)
There are 4745 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[24]/Q (HIGH)
There are 4745 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[25]/Q (HIGH)
There are 4745 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[26]/Q (HIGH)
There are 4745 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[27]/Q (HIGH)
There are 4745 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[28]/Q (HIGH)
There are 4745 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[29]/Q (HIGH)
There are 4745 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[2]/Q (HIGH)
There are 4745 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[30]/Q (HIGH)
There are 4745 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[31]/Q (HIGH)
There are 4745 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[3]/Q (HIGH)
There are 4745 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[4]/Q (HIGH)
There are 4745 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[5]/Q (HIGH)
There are 4745 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[6]/Q (HIGH)
There are 4745 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[7]/Q (HIGH)
There are 4745 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[8]/Q (HIGH)
There are 4745 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[9]/Q (HIGH)
There are 278 register/latch pins with no clock driven by root clock pin: u_Controller/Interpreter/core_reset_reg/Q (HIGH)
There are 76 register/latch pins with no clock driven by root clock pin: u_Controller/Interpreter/memory_mux_selector_reg_rep/Q (HIGH)
There are 76 register/latch pins with no clock driven by root clock pin: u_Controller/Interpreter/memory_mux_selector_reg_rep__0/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_f0_3th_core/CSR/CSR_updating_logic[0].TMR_CMP_MEPC/tmr_reg_o_int_data_A_reg[9]/Q (HIGH)
There are 79 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/CSR/CSR_updating_logic[0].TMR_CMP_MIP/tmr_reg_o_int_data_A_reg[3]/Q (HIGH)
There are 175 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/CSR/CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[3]_C/Q (HIGH)
There are 175 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/CSR/CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[3]_LDC/Q (HIGH)
There are 175 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/CSR/CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[3]_P/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_f0_3th_core/CSR/CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[7]_C/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_f0_3th_core/CSR/CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[7]_LDC/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_f0_3th_core/CSR/CSR_updating_logic[0].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[7]_P/Q (HIGH)
There are 99 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/CSR/CSR_updating_logic[0].sTMR_CMP_csr_access_denied/tmr_sreg_o_int_data_A_reg/Q (HIGH)
There are 177 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/CSR/CSR_updating_logic[0].sTMR_CMP_csr_instr_done/tmr_sreg_o_int_data_A_reg/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_f0_3th_core/CSR/CSR_updating_logic[1].TMR_CMP_MEPC/tmr_reg_o_int_data_A_reg[9]/Q (HIGH)
There are 79 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/CSR/CSR_updating_logic[1].TMR_CMP_MIP/tmr_reg_o_int_data_A_reg[3]/Q (HIGH)
There are 176 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/CSR/CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[3]_C/Q (HIGH)
There are 176 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/CSR/CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[3]_LDC/Q (HIGH)
There are 176 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/CSR/CSR_updating_logic[1].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[3]_P/Q (HIGH)
There are 99 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/CSR/CSR_updating_logic[1].sTMR_CMP_csr_access_denied/tmr_sreg_o_int_data_A_reg/Q (HIGH)
There are 177 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/CSR/CSR_updating_logic[1].sTMR_CMP_csr_instr_done/tmr_sreg_o_int_data_A_reg/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_f0_3th_core/CSR/CSR_updating_logic[2].TMR_CMP_MEPC/tmr_reg_o_int_data_A_reg[9]/Q (HIGH)
There are 276 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/CSR/CSR_updating_logic[2].TMR_CMP_MIP/tmr_reg_o_int_data_A_reg[3]/Q (HIGH)
There are 275 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/CSR/CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[3]_C/Q (HIGH)
There are 275 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/CSR/CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[3]_LDC/Q (HIGH)
There are 275 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/CSR/CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[3]_P/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_f0_3th_core/CSR/CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[7]_C/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_f0_3th_core/CSR/CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[7]_LDC/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_f0_3th_core/CSR/CSR_updating_logic[2].TMR_CMP_MSTATUS/tmr_reg_o_int_data_A_reg[7]_P/Q (HIGH)
There are 99 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/CSR/CSR_updating_logic[2].sTMR_CMP_csr_access_denied/tmr_sreg_o_int_data_A_reg/Q (HIGH)
There are 177 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/CSR/CSR_updating_logic[2].sTMR_CMP_csr_instr_done/tmr_sreg_o_int_data_A_reg/Q (HIGH)
There are 76 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/DBG/FSM_sequential_state_DBU_reg[0]/Q (HIGH)
There are 76 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/DBG/FSM_sequential_state_DBU_reg[1]/Q (HIGH)
There are 76 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/DBG/FSM_sequential_state_DBU_reg[2]/Q (HIGH)
There are 275 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/Replicated_TMR_reg_gen[0].TMR_CMP_flush_cycle_count/tmr_ireg_o_int_data_A_reg[0]/Q (HIGH)
There are 275 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/Replicated_TMR_reg_gen[0].TMR_CMP_flush_cycle_count/tmr_ireg_o_int_data_A_reg[1]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/Replicated_TMR_reg_gen[0].TMR_CMP_pc_except_value/tmr_reg_o_int_data_A_reg[9]/Q (HIGH)
There are 275 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/Replicated_TMR_reg_gen[1].TMR_CMP_flush_cycle_count/tmr_ireg_o_int_data_A_reg[0]/Q (HIGH)
There are 275 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/Replicated_TMR_reg_gen[1].TMR_CMP_flush_cycle_count/tmr_ireg_o_int_data_A_reg[1]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/Replicated_TMR_reg_gen[1].TMR_CMP_pc_except_value/tmr_reg_o_int_data_A_reg[9]/Q (HIGH)
There are 275 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/Replicated_TMR_reg_gen[2].TMR_CMP_flush_cycle_count/tmr_ireg_o_int_data_A_reg[0]/Q (HIGH)
There are 275 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/Replicated_TMR_reg_gen[2].TMR_CMP_flush_cycle_count/tmr_ireg_o_int_data_A_reg[1]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/Replicated_TMR_reg_gen[2].TMR_CMP_pc_except_value/tmr_reg_o_int_data_A_reg[9]/Q (HIGH)
There are 175 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_RS1_Data_IE/tmr_reg_o_int_data_A_reg[0]/Q (HIGH)
There are 175 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_RS1_Data_IE/tmr_reg_o_int_data_A_reg[1]/Q (HIGH)
There are 175 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_amo_load/tmr_sreg_o_int_data_A_reg/Q (HIGH)
There are 175 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_amo_load_skip/tmr_sreg_o_int_data_A_reg/Q (HIGH)
There are 175 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_amo_store_lat/tmr_sreg_o_int_data_A_reg/Q (HIGH)
There are 4 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_csr_addr_i/tmr_reg_o_int_data_A_reg[0]/Q (HIGH)
There are 4 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_csr_addr_i/tmr_reg_o_int_data_A_reg[10]/Q (HIGH)
There are 4 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_csr_addr_i/tmr_reg_o_int_data_A_reg[11]/Q (HIGH)
There are 4 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_csr_addr_i/tmr_reg_o_int_data_A_reg[1]/Q (HIGH)
There are 4 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_csr_addr_i/tmr_reg_o_int_data_A_reg[2]/Q (HIGH)
There are 4 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_csr_addr_i/tmr_reg_o_int_data_A_reg[3]/Q (HIGH)
There are 4 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_csr_addr_i/tmr_reg_o_int_data_A_reg[4]/Q (HIGH)
There are 4 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_csr_addr_i/tmr_reg_o_int_data_A_reg[5]/Q (HIGH)
There are 4 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_csr_addr_i/tmr_reg_o_int_data_A_reg[6]/Q (HIGH)
There are 4 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_csr_addr_i/tmr_reg_o_int_data_A_reg[7]/Q (HIGH)
There are 4 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_csr_addr_i/tmr_reg_o_int_data_A_reg[8]/Q (HIGH)
There are 4 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_csr_addr_i/tmr_reg_o_int_data_A_reg[9]/Q (HIGH)
There are 4 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_csr_instr_req/tmr_sreg_o_int_data_A_reg/Q (HIGH)
There are 3 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_csr_op_i/tmr_reg_o_int_data_A_reg[0]_rep/Q (HIGH)
There are 4 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_csr_op_i/tmr_reg_o_int_data_A_reg[0]_rep__3/Q (HIGH)
There are 3 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_csr_op_i/tmr_reg_o_int_data_A_reg[1]/Q (HIGH)
There are 4 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_csr_op_i/tmr_reg_o_int_data_A_reg[1]_rep__2/Q (HIGH)
There are 3 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_csr_wdata_i/tmr_reg_o_int_data_A_reg[9]/Q (HIGH)
There are 76 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_data_we_o_lat/tmr_sreg_o_int_data_A_reg/Q (HIGH)
There are 192 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_decoded_instruction_IE/tmr_reg_o_int_data_A_reg[21]/Q (HIGH)
There are 192 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_decoded_instruction_IE/tmr_reg_o_int_data_A_reg[22]/Q (HIGH)
There are 192 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_decoded_instruction_IE/tmr_reg_o_int_data_A_reg[23]/Q (HIGH)
There are 192 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_decoded_instruction_IE/tmr_reg_o_int_data_A_reg[24]/Q (HIGH)
There are 192 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_decoded_instruction_IE/tmr_reg_o_int_data_A_reg[25]/Q (HIGH)
There are 192 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_decoded_instruction_IE/tmr_reg_o_int_data_A_reg[26]/Q (HIGH)
There are 192 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_decoded_instruction_IE/tmr_reg_o_int_data_A_reg[27]/Q (HIGH)
There are 192 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_decoded_instruction_IE/tmr_reg_o_int_data_A_reg[28]/Q (HIGH)
There are 175 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_decoded_instruction_IE/tmr_reg_o_int_data_A_reg[29]/Q (HIGH)
There are 175 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_decoded_instruction_IE/tmr_reg_o_int_data_A_reg[30]/Q (HIGH)
There are 175 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_decoded_instruction_IE/tmr_reg_o_int_data_A_reg[31]/Q (HIGH)
There are 76 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_decoded_instruction_IE/tmr_reg_o_int_data_A_reg[32]/Q (HIGH)
There are 76 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_decoded_instruction_IE/tmr_reg_o_int_data_A_reg[33]/Q (HIGH)
There are 175 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_decoded_instruction_IE/tmr_reg_o_int_data_A_reg[34]/Q (HIGH)
There are 175 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_decoded_instruction_IE/tmr_reg_o_int_data_A_reg[35]/Q (HIGH)
There are 76 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_decoded_instruction_IE/tmr_reg_o_int_data_A_reg[36]/Q (HIGH)
There are 99 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_decoded_instruction_IE/tmr_reg_o_int_data_A_reg[39]/Q (HIGH)
There are 99 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_decoded_instruction_IE/tmr_reg_o_int_data_A_reg[41]/Q (HIGH)
There are 99 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_decoded_instruction_IE/tmr_reg_o_int_data_A_reg[42]/Q (HIGH)
There are 76 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_decoded_instruction_IE/tmr_reg_o_int_data_A_reg[43]/Q (HIGH)
There are 76 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_decoded_instruction_IE/tmr_reg_o_int_data_A_reg[44]/Q (HIGH)
There are 76 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_decoded_instruction_IE/tmr_reg_o_int_data_A_reg[45]/Q (HIGH)
There are 76 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_decoded_instruction_IE/tmr_reg_o_int_data_A_reg[46]/Q (HIGH)
There are 76 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_decoded_instruction_IE/tmr_reg_o_int_data_A_reg[47]/Q (HIGH)
There are 76 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_decoded_instruction_IE/tmr_reg_o_int_data_A_reg[48]/Q (HIGH)
There are 175 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_decoded_instruction_IE/tmr_reg_o_int_data_A_reg[49]/Q (HIGH)
There are 99 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_decoded_instruction_IE/tmr_reg_o_int_data_A_reg[51]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_IE/tmr_ireg_o_int_data_A_reg[0]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_IE/tmr_ireg_o_int_data_A_reg[0]_rep/Q (HIGH)
There are 33 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_IE/tmr_ireg_o_int_data_A_reg[0]_rep__0/Q (HIGH)
There are 275 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_IE/tmr_ireg_o_int_data_A_reg[0]_rep__1/Q (HIGH)
There are 34 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_IE/tmr_ireg_o_int_data_A_reg[0]_rep__2/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_IE/tmr_ireg_o_int_data_A_reg[1]/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_IE/tmr_ireg_o_int_data_A_reg[1]_rep/Q (HIGH)
There are 33 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_IE/tmr_ireg_o_int_data_A_reg[1]_rep__0/Q (HIGH)
There are 275 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_IE/tmr_ireg_o_int_data_A_reg[1]_rep__1/Q (HIGH)
There are 34 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_IE/tmr_ireg_o_int_data_A_reg[1]_rep__2/Q (HIGH)
There are 4 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_to_csr/tmr_ireg_o_int_data_A_reg[0]/Q (HIGH)
There are 4 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_to_csr/tmr_ireg_o_int_data_A_reg[1]/Q (HIGH)
There are 275 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_instr_rvalid_IE/tmr_sreg_o_int_data_A_reg/Q (HIGH)
There are 34 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_instr_rvalid_state/tmr_sreg_o_int_data_A_reg/Q (HIGH)
There are 3 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_instr_word_IE/tmr_reg_o_int_data_A_reg[15]_C/Q (HIGH)
There are 3 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_instr_word_IE/tmr_reg_o_int_data_A_reg[16]_C/Q (HIGH)
There are 3 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_instr_word_IE/tmr_reg_o_int_data_A_reg[17]_C/Q (HIGH)
There are 3 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_instr_word_IE/tmr_reg_o_int_data_A_reg[18]_C/Q (HIGH)
There are 3 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_instr_word_IE/tmr_reg_o_int_data_A_reg[19]_C/Q (HIGH)
There are 175 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_instr_word_IE/tmr_reg_o_int_data_A_reg[20]_C/Q (HIGH)
There are 175 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_instr_word_IE/tmr_reg_o_int_data_A_reg[21]_C/Q (HIGH)
There are 175 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_instr_word_IE/tmr_reg_o_int_data_A_reg[7]_C/Q (HIGH)
There are 175 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_instr_word_IE/tmr_reg_o_int_data_A_reg[8]_C/Q (HIGH)
There are 99 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_pass_BEQ_ID/tmr_sreg_o_int_data_A_reg/Q (HIGH)
There are 99 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_pass_BGEU_ID/tmr_sreg_o_int_data_A_reg/Q (HIGH)
There are 99 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_pass_BGE_ID/tmr_sreg_o_int_data_A_reg/Q (HIGH)
There are 99 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_pass_BLTU_ID/tmr_sreg_o_int_data_A_reg/Q (HIGH)
There are 99 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_pass_BLT_ID/tmr_sreg_o_int_data_A_reg/Q (HIGH)
There are 99 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_pass_BNE_ID/tmr_sreg_o_int_data_A_reg/Q (HIGH)
There are 3 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_pc_IE/tmr_reg_o_int_data_A_reg[10]/Q (HIGH)
There are 3 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_pc_IE/tmr_reg_o_int_data_A_reg[11]/Q (HIGH)
There are 3 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_pc_IE/tmr_reg_o_int_data_A_reg[9]/Q (HIGH)
There are 76 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/TMR_CMP_sw_mip/tmr_sreg_o_int_data_A_reg/Q (HIGH)
There are 275 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/state_IE_reg[0]/Q (HIGH)
There are 275 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/state_IE_reg[1]/Q (HIGH)
There are 275 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Pipe/state_IE_reg[2]/Q (HIGH)
There are 3 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Prg_Ctr/TMR_CMP_harc_IF/tmr_ireg_o_int_data_A_reg[0]_C/Q (HIGH)
There are 3 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Prg_Ctr/TMR_CMP_harc_IF/tmr_ireg_o_int_data_A_reg[1]_C/Q (HIGH)
There are 3 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Prg_Ctr/TMR_CMP_harc_IF/tmr_ireg_o_int_data_A_reg[1]_LDC/Q (HIGH)
There are 3 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Prg_Ctr/TMR_CMP_harc_IF/tmr_ireg_o_int_data_A_reg[1]_P/Q (HIGH)
There are 3 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Prg_Ctr/pc_update_logic[0].TMR_CMP_served_except_condition/tmr_sreg_o_int_data_A_reg/Q (HIGH)
There are 3 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Prg_Ctr/pc_update_logic[0].TMR_CMP_served_mret_condition/tmr_sreg_o_int_data_A_reg/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_f0_3th_core/Prg_Ctr/pc_update_logic[0].TMR_CMP_taken_branch_pending/tmr_sreg_o_int_data_A_reg/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_f0_3th_core/Prg_Ctr/pc_update_logic[0].TMR_CMP_wfi_condition_pending/tmr_sreg_o_int_data_A_reg/Q (HIGH)
There are 3 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Prg_Ctr/pc_update_logic[1].TMR_CMP_served_except_condition/tmr_sreg_o_int_data_A_reg/Q (HIGH)
There are 3 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Prg_Ctr/pc_update_logic[1].TMR_CMP_served_mret_condition/tmr_sreg_o_int_data_A_reg/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_f0_3th_core/Prg_Ctr/pc_update_logic[1].TMR_CMP_taken_branch_pending/tmr_sreg_o_int_data_A_reg/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_f0_3th_core/Prg_Ctr/pc_update_logic[1].TMR_CMP_wfi_condition_pending/tmr_sreg_o_int_data_A_reg/Q (HIGH)
There are 2 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Prg_Ctr/pc_update_logic[2].TMR_CMP_served_except_condition/tmr_sreg_o_int_data_A_reg/Q (HIGH)
There are 3 register/latch pins with no clock driven by root clock pin: u_klessydra_f0_3th_core/Prg_Ctr/pc_update_logic[2].TMR_CMP_served_mret_condition/tmr_sreg_o_int_data_A_reg/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_f0_3th_core/Prg_Ctr/pc_update_logic[2].TMR_CMP_taken_branch_pending/tmr_sreg_o_int_data_A_reg/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_klessydra_f0_3th_core/Prg_Ctr/pc_update_logic[2].TMR_CMP_wfi_condition_pending/tmr_sreg_o_int_data_A_reg/Q (HIGH)
2. checking constant_clock (0)
------------------------------
There are 0 register/latch pins with constant_clock.
3. checking pulse_width_clock (0)
---------------------------------
There are 0 register/latch pins which need pulse_width check
4. checking unconstrained_internal_endpoints (31431)
----------------------------------------------------
There are 31431 pins that are not constrained for maximum delay. (HIGH)
There are 0 pins that are not constrained for maximum delay due to constant clock.
5. checking no_input_delay (1)
------------------------------
There is 1 input port with no input delay specified. (HIGH)
There are 0 input ports with no input delay but user has a false path constraint.
6. checking no_output_delay (1)
-------------------------------
There is 1 port with no output delay specified. (HIGH)
There are 0 ports with no output delay but user has a false path constraint
There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
7. checking multiple_clock (0)
------------------------------
There are 0 register/latch pins with multiple clocks.
8. checking generated_clocks (0)
--------------------------------
There are 0 generated clocks that are not connected to a clock source.
9. checking loops (0)
---------------------
There are 0 combinational loops in the design.
10. checking partial_input_delay (0)
------------------------------------
There are 0 input ports with partial input delay specified.
11. checking partial_output_delay (0)
-------------------------------------
There are 0 ports with partial output delay specified.
12. checking latch_loops (0)
----------------------------
There are 0 combinational latch loops in the design through latch input
------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------
WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
8.522 0.000 0 1 0.447 0.000 0 1 4.500 0.000 0 2
All user specified timing constraints are met.
------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------
Clock Waveform(ns) Period(ns) Frequency(MHz)
----- ------------ ---------- --------------
sck {0.000 50.000} 100.000 10.000
sys_clk_pin {0.000 5.000} 10.000 100.000
------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------
Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
sys_clk_pin 8.522 0.000 0 1 0.447 0.000 0 1 4.500 0.000 0 2
------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------
From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
# report_route_status -file digilent_arty_a7_route_status.rpt
# report_drc -file digilent_arty_a7_drc.rpt
Command: report_drc -file digilent_arty_a7_drc.rpt
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/eda/vivado/Vivado/2023.2/data/ip'.
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /var/jenkins_home/workspace/F03x/F03x/digilent_arty_a7_drc.rpt.
report_drc completed successfully
# report_timing_summary -datasheet -max_paths 10 -file digilent_arty_a7_timing.rpt
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
# report_power -file digilent_arty_a7_power.rpt
Command: report_power -file digilent_arty_a7_power.rpt
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
0 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
# write_bitstream -force "digilent_arty_a7_100t.bit"
Command: write_bitstream -force digilent_arty_a7_100t.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 8 threads
WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND
set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0
Refer to the device configuration user guide for more information.
WARNING: [DRC PDRC-153] Gated clock check: Net u_Controller/Interpreter/core_reset_reg_10 is a gated clock net sourced by a combinational pin u_Controller/Interpreter/tmr_reg_o_int_data_A_reg[3]_LDC_i_1__0/O, cell u_Controller/Interpreter/tmr_reg_o_int_data_A_reg[3]_LDC_i_1__0. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
WARNING: [DRC PDRC-153] Gated clock check: Net u_Controller/Interpreter/core_reset_reg_12 is a gated clock net sourced by a combinational pin u_Controller/Interpreter/tmr_reg_o_int_data_A_reg[7]_LDC_i_1__0/O, cell u_Controller/Interpreter/tmr_reg_o_int_data_A_reg[7]_LDC_i_1__0. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
WARNING: [DRC PDRC-153] Gated clock check: Net u_Controller/Interpreter/core_reset_reg_16 is a gated clock net sourced by a combinational pin u_Controller/Interpreter/tmr_reg_o_int_data_A_reg[3]_LDC_i_1__1/O, cell u_Controller/Interpreter/tmr_reg_o_int_data_A_reg[3]_LDC_i_1__1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
WARNING: [DRC PDRC-153] Gated clock check: Net u_Controller/Interpreter/core_reset_reg_18 is a gated clock net sourced by a combinational pin u_Controller/Interpreter/tmr_reg_o_int_data_A_reg[7]_LDC_i_1__1/O, cell u_Controller/Interpreter/tmr_reg_o_int_data_A_reg[7]_LDC_i_1__1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
WARNING: [DRC PDRC-153] Gated clock check: Net u_Controller/Interpreter/core_reset_reg_6 is a gated clock net sourced by a combinational pin u_Controller/Interpreter/tmr_reg_o_int_data_A_reg[3]_LDC_i_1/O, cell u_Controller/Interpreter/tmr_reg_o_int_data_A_reg[3]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
WARNING: [DRC PDRC-153] Gated clock check: Net u_Controller/Interpreter/core_reset_reg_8 is a gated clock net sourced by a combinational pin u_Controller/Interpreter/tmr_reg_o_int_data_A_reg[7]_LDC_i_1/O, cell u_Controller/Interpreter/tmr_reg_o_int_data_A_reg[7]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
WARNING: [DRC PDRC-153] Gated clock check: Net u_klessydra_f0_3th_core/CSR/CSR_updating_logic[0].TMR_CMP_MIP/CSR_updating_logic[0].trap_hndlr_reg0 is a gated clock net sourced by a combinational pin u_klessydra_f0_3th_core/CSR/CSR_updating_logic[0].TMR_CMP_MIP/CSR_updating_logic[0].trap_hndlr_reg[0]_i_1/O, cell u_klessydra_f0_3th_core/CSR/CSR_updating_logic[0].TMR_CMP_MIP/CSR_updating_logic[0].trap_hndlr_reg[0]_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
WARNING: [DRC PDRC-153] Gated clock check: Net u_klessydra_f0_3th_core/CSR/CSR_updating_logic[2].TMR_CMP_MIP/CSR_updating_logic[2].trap_hndlr_reg0 is a gated clock net sourced by a combinational pin u_klessydra_f0_3th_core/CSR/CSR_updating_logic[2].TMR_CMP_MIP/CSR_updating_logic[2].trap_hndlr_reg[2]_i_1/O, cell u_klessydra_f0_3th_core/CSR/CSR_updating_logic[2].TMR_CMP_MIP/CSR_updating_logic[2].trap_hndlr_reg[2]_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
WARNING: [DRC PDRC-153] Gated clock check: Net u_klessydra_f0_3th_core/Pipe/TMR_CMP_csr_op_i/CSR_updating_logic[1].trap_hndlr_reg0 is a gated clock net sourced by a combinational pin u_klessydra_f0_3th_core/Pipe/TMR_CMP_csr_op_i/CSR_updating_logic[1].trap_hndlr_reg[1]_i_1/O, cell u_klessydra_f0_3th_core/Pipe/TMR_CMP_csr_op_i/CSR_updating_logic[1].trap_hndlr_reg[1]_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
WARNING: [DRC PDRC-153] Gated clock check: Net u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_IE/core_reset_reg_0 is a gated clock net sourced by a combinational pin u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_IE/pc_update_logic[0].wfi_condition_pending_wire_reg[0]_i_2/O, cell u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_IE/pc_update_logic[0].wfi_condition_pending_wire_reg[0]_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
WARNING: [DRC PDRC-153] Gated clock check: Net u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_IE/core_reset_reg_1 is a gated clock net sourced by a combinational pin u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_IE/pc_update_logic[1].wfi_condition_pending_wire_reg[1]_i_2/O, cell u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_IE/pc_update_logic[1].wfi_condition_pending_wire_reg[1]_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
WARNING: [DRC PDRC-153] Gated clock check: Net u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_IE/core_reset_reg_2 is a gated clock net sourced by a combinational pin u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_IE/pc_update_logic[2].wfi_condition_pending_wire_reg[2]_i_2/O, cell u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_IE/pc_update_logic[2].wfi_condition_pending_wire_reg[2]_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 13 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Writing bitstream ./digilent_arty_a7_100t.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-83] Releasing license: Implementation
9 Infos, 13 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:23 . Memory (MB): peak = 3321.926 ; gain = 241.465 ; free physical = 5090 ; free virtual = 26998
# exit
INFO: [Common 17-206] Exiting Vivado at Sat Apr 26 22:08:19 2025...
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash digilent_arty_a7_100t)
[Pipeline] dir
Running in /var/jenkins_home/workspace/F03x/F03x
[Pipeline] {
[Pipeline] echo
Flashing FPGA digilent_arty_a7_100t.
[Pipeline] sh
+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p F03x -b digilent_arty_a7_100t -l
Makefile executed successfully.
Makefile output:
Flashing the FPGA...
/eda/oss-cad-suite/bin/openFPGALoader -b arty_a7_100t digilent_arty_a7_100t.bit
empty
Jtag frequency : requested 10.00MHz -> real 10.00MHz
Open file DONE
Parse file DONE
load program
Load SRAM: [================ ] 31.00%
Load SRAM: [================================ ] 63.00%
Load SRAM: [================================================ ] 95.00%
Load SRAM: [===================================================] 100.00%
Done
Shift IR 35
ir: 1 isc_done 1 isc_ena 0 init 1 done 1
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Test digilent_arty_a7_100t)
[Pipeline] echo
Testing FPGA digilent_arty_a7_100t.
[Pipeline] sh
+ echo Test for FPGA in /dev/ttyUSB1
Test for FPGA in /dev/ttyUSB1
[Pipeline] sh
+ python3 /eda/processor_ci_tests/main.py -b 115200 -s 2 -c /eda/processor_ci_tests/config.json --p /dev/ttyUSB1 -m rv32i -k 0x41525459 -ctm
32
Connected to FPGA with ID: b'ARTY'
Checking for sync keyword...
Sync keyword matched.
Testsuite configurated.
Running tests: RV32I in /eda/processor_ci_tests/tests/RV32I
Running basic tests in /eda/processor_ci_tests/tests/RV32I/basic, with breakpoint 60
Running test: 000-addi.hex
Running test: 001-sw.hex
Running test: 002-slti.hex
Running test: 003-sltiu.hex
Running test: 004-xori.hex
Running test: 005-ori.hex
Running test: 006-andi.hex
Running test: 007-slli.hex
Running test: 008-srli.hex
Running test: 009-srai.hex
Running test: 010-lui.hex
Running test: 011-auipc.hex
Running test: 012-jal.hex
Running test: 013-jalr.hex
Running test: 014-beq.hex
Running test: 015-bne.hex
Running test: 016-blt.hex
Running test: 017-bge.hex
Running test: 018-bltu.hex
Running test: 019-bgeu.hex
Running test: 020-lb.hex
Running test: 021-lh.hex
Running test: 022-lw.hex
Running test: 023-lbu.hex
Running test: 024-lhu.hex
Running test: 025-sb.hex
Running test: 026-sh.hex
Running test: 027-add.hex
Running test: 028-sub.hex
Running test: 029-sll.hex
Running test: 030-slt.hex
Running test: 031-sltu.hex
Running test: 032-xor.hex
Running test: 033-srl.hex
Running test: 034-sra.hex
Running test: 035-or.hex
Running test: 036-and.hex
Running test: 037-fence.hex
Running test: 038-ecall.hex
Running test: 039-ebreak.hex
Running test: 040-timeout.hex
Running test: 041-forwarding.hex
Running test: 042-forwarding-lw.hex
JUnit XML report generated: test_results_1745719712.1410398.xml
All tests finished.
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Lock released on resource [Resource: digilent_arty_a7_100t]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Declarative: Post Actions)
[Pipeline] junit
Recording test results
[Checks API] No suitable checks publisher found.
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
Finished: UNSTABLE
![[Jenkins]](/jenkins/static/ee6d6826/images/svgs/logo.svg){kind=logo}
