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Start of Pipeline - (8 min 37 sec in block)
node - (8 min 36 sec in block)
node block - (28 sec in block)
stage - (2.4 sec in block)Git Clone
stage block (Git Clone) - (1.8 sec in block)
sh - (0.6 sec in self)rm -rf F03x
sh - (0.9 sec in self)git clone --recursive --depth=1 https://github.com/klessydra/F03x F03x
stage - (10 sec in block)Simulation
stage block (Simulation) - (9.7 sec in block)
dir - (9.4 sec in block)F03x
dir block - (9.1 sec in block)
sh - (8.9 sec in self)/eda/oss-cad-suite/bin/ghdl -a --std=08 klessydra-f0-3th/PKG_RiscV_Klessydra_thread_parameters.vhd klessydra-f0-3th/PKG_RiscV_Klessydra.vhd klessydra-f0-3th/TMR_REG_PKG.vhd klessydra-f0-3th/CMP-TMR_REG.vhd klessydra-f0-3th/RTL-CSR_Unit_TMR.vhd klessydra-f0-3th/RTL-Debug_Unit.vhd klessydra-f0-3th/RTL-Processing_Pipeline_TMR.vhd klessydra-f0-3th/RTL-Program_Counter_unit_TMR.vhd klessydra-f0-3th/STR-Klessydra_top.vhd
stage - (1.7 sec in block)Utilities
stage block (Utilities) - (1.2 sec in block)
dir - (0.89 sec in block)F03x
dir block - (0.6 sec in block)
sh - (0.4 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config.json -o /jenkins/processor_ci_utils/labels
stage - (13 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (12 sec in block)
parallel - (12 sec in block)
parallel block (Branch: colorlight_i9) - (60 ms in block)
stage - (10 sec in block)colorlight_i9
stage block (colorlight_i9) - (9.6 sec in block)
lock - (8.8 sec in block)colorlight_i9
lock block - (7.4 sec in block)
stage - (3.5 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (2.2 sec in block)
dir - (1.5 sec in block)F03x
dir block - (1.1 sec in block)
echo - (0.15 sec in self)Starting synthesis for FPGA colorlight_i9.
sh - (0.65 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p F03x -b colorlight_i9
stage - (1.7 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (0.6 sec in block)
getContext - (0.17 sec in self)
stage - (1.2 sec in block)Test colorlight_i9
stage block (Test colorlight_i9) - (0.64 sec in block)
getContext - (0.16 sec in self)
parallel block (Branch: digilent_arty_a7_100t) - (11 sec in block)
stage - (10 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (9.9 sec in block)
lock - (8.9 sec in block)digilent_arty_a7_100t
lock block - (7.5 sec in block)
stage - (3.5 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (2.8 sec in block)
dir - (2.1 sec in block)F03x
dir block - (1.6 sec in block)
echo - (0.16 sec in self)Starting synthesis for FPGA digilent_arty_a7_100t.
sh - (1 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p F03x -b digilent_arty_a7_100t
stage - (1.8 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (0.72 sec in block)
getContext - (0.15 sec in self)
stage - (1.4 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (0.68 sec in block)
getContext - (0.16 sec in self)
stage - (0.8 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.54 sec in block)
junit - (0.28 sec in self)**/test-reports/*.xml