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Start of Pipeline - (4 min 51 sec in block)
node - (4 min 50 sec in block)
node block - (4 min 50 sec in block)
stage - (2.6 sec in block)Git Clone
stage block (Git Clone) - (2.2 sec in block)
sh - (0.48 sec in self)rm -rf *.xml
sh - (0.47 sec in self)rm -rf F03x
sh - (1 sec in self)git clone --recursive --depth=1 https://github.com/klessydra/F03x F03x
stage - (5.5 sec in block)Simulation
stage block (Simulation) - (5 sec in block)
dir - (4.6 sec in block)F03x
dir block - (4.3 sec in block)
sh - (4.1 sec in self)/eda/oss-cad-suite/bin/ghdl -a --std=08 klessydra-f0-3th/PKG_RiscV_Klessydra_thread_parameters.vhd klessydra-f0-3th/PKG_RiscV_Klessydra.vhd klessydra-f0-3th/TMR_REG_PKG.vhd klessydra-f0-3th/CMP-TMR_REG.vhd klessydra-f0-3th/RTL-CSR_Unit_TMR.vhd klessydra-f0-3th/RTL-Debug_Unit.vhd klessydra-f0-3th/RTL-Processing_Pipeline_TMR.vhd klessydra-f0-3th/RTL-Program_Counter_unit_TMR.vhd klessydra-f0-3th/STR-Klessydra_top.vhd
stage - (1.7 sec in block)Utilities
stage block (Utilities) - (1.2 sec in block)
dir - (0.85 sec in block)F03x
dir block - (0.6 sec in block)
sh - (0.4 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config -o /jenkins/processor_ci_utils/labels
stage - (4 min 38 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (4 min 38 sec in block)
parallel - (4 min 38 sec in block)
parallel block (Branch: digilent_arty_a7_100t) - (4 min 37 sec in block)
stage - (4 min 37 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (4 min 37 sec in block)
lock - (4 min 36 sec in block)digilent_arty_a7_100t
lock block - (4 min 36 sec in block)
stage - (4 min 23 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (4 min 22 sec in block)
dir - (4 min 22 sec in block)F03x
dir block - (4 min 22 sec in block)
echo - (0.17 sec in self)Starting synthesis for FPGA digilent_arty_a7_100t.
sh - (4 min 21 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p F03x -b digilent_arty_a7_100t
stage - (6 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (5.6 sec in block)
dir - (5.2 sec in block)F03x
dir block - (4.9 sec in block)
echo - (0.17 sec in self)Flashing FPGA digilent_arty_a7_100t.
sh - (4.5 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p F03x -b digilent_arty_a7_100t -l
stage - (6.7 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (6.4 sec in block)
echo - (0.17 sec in self)Testing FPGA digilent_arty_a7_100t.
sh - (0.44 sec in self)echo "Test for FPGA in /dev/ttyUSB1"
sh - (5.6 sec in self)python3 /eda/processor_ci_tests/main.py -b 115200 -s 2 -c /eda/processor_ci_tests/config.json --p /dev/ttyUSB1 -m rv32i -k 0x41525459 -ctm
stage - (0.81 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.56 sec in block)
junit - (0.31 sec in self)**/*.xml