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Start of Pipeline - (6 min 38 sec in block)
node - (6 min 36 sec in block)
node block - (6 min 36 sec in block)
stage - (2.5 sec in block)Git Clone
stage block (Git Clone) - (2 sec in block)
sh - (0.5 sec in self)rm -rf F03x
sh - (1.2 sec in self)git clone --recursive https://github.com/klessydra/F03x F03x
stage - (2.6 sec in block)Simulation
stage block (Simulation) - (2 sec in block)
dir - (1.5 sec in block)F03x
dir block - (1.3 sec in block)
sh - (1 sec in self)ghdl -a --std=08 klessydra-f0-3th/PKG_RiscV_Klessydra_thread_parameters.vhd klessydra-f0-3th/PKG_RiscV_Klessydra.vhd klessydra-f0-3th/TMR_REG_PKG.vhd klessydra-f0-3th/CMP-TMR_REG.vhd klessydra-f0-3th/RTL-CSR_Unit_TMR.vhd klessydra-f0-3th/RTL-Debug_Unit.vhd klessydra-f0-3th/RTL-Processing_Pipeline_TMR.vhd klessydra-f0-3th/RTL-Program_Counter_unit_TMR.vhd klessydra-f0-3th/STR-Klessydra_top.vhd
stage - (6 min 28 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (6 min 28 sec in block)
parallel - (6 min 27 sec in block)
parallel block (Branch: colorlight_i9) - (67 ms in block)
stage - (1 min 39 sec in block)colorlight_i9
stage block (colorlight_i9) - (1 min 39 sec in block)
lock - (1 min 38 sec in block)colorlight_i9
lock block - (5.7 sec in block)
stage - (3.3 sec in block)Síntese e PnR
stage block (Síntese e PnR) - (2.5 sec in block)
dir - (1.7 sec in block)F03x
dir block - (1.3 sec in block)
echo - (0.2 sec in self)Iniciando síntese para FPGA colorlight_i9.
sh - (0.75 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p F03x -b colorlight_i9
stage - (1 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (0.4 sec in block)
getContext - (0.16 sec in self)
stage - (0.74 sec in block)Teste colorlight_i9
stage block (Teste colorlight_i9) - (0.41 sec in block)
getContext - (0.16 sec in self)
parallel block (Branch: digilent_nexys4_ddr) - (6 min 26 sec in block)
stage - (6 min 25 sec in block)digilent_nexys4_ddr
stage block (digilent_nexys4_ddr) - (6 min 25 sec in block)
lock - (6 min 23 sec in block)digilent_nexys4_ddr
lock block - (1 min 13 sec in block)
stage - (1 min 10 sec in block)Síntese e PnR
stage block (Síntese e PnR) - (1 min 10 sec in block)
dir - (1 min 9 sec in block)F03x
dir block - (1 min 8 sec in block)
echo - (0.34 sec in self)Iniciando síntese para FPGA digilent_nexys4_ddr.
sh - (1 min 8 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p F03x -b digilent_nexys4_ddr
stage - (1.1 sec in block)Flash digilent_nexys4_ddr
stage block (Flash digilent_nexys4_ddr) - (0.44 sec in block)
getContext - (0.2 sec in self)
stage - (0.73 sec in block)Teste digilent_nexys4_ddr
stage block (Teste digilent_nexys4_ddr) - (0.4 sec in block)
getContext - (0.19 sec in self)
stage - (1.6 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (1.4 sec in block)
dir - (0.95 sec in block)F03x
dir block - (0.7 sec in block)
sh - (0.48 sec in self)rm -rf *