Started by timer [Pipeline] Start of Pipeline [Pipeline] node Running on Jenkins in /var/lib/jenkins/workspace/F03x [Pipeline] { [Pipeline] stage [Pipeline] { (Git Clone) [Pipeline] sh + rm -Rf F03x/ build/ [Pipeline] sh + git clone https://github.com/klessydra/F03x.git Cloning into 'F03x'... [Pipeline] sh + cd F03x [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (GHDL) [Pipeline] sh + /eda/oss-cad-suite/bin/ghdl -a --std=08 F03x/klessydra-f0-3th/PKG_RiscV_Klessydra_thread_parameters.vhd F03x/klessydra-f0-3th/PKG_RiscV_Klessydra.vhd F03x/klessydra-f0-3th/TMR_REG_PKG.vhd F03x/klessydra-f0-3th/RTL-CSR_Unit_TMR.vhd F03x/klessydra-f0-3th/RTL-Debug_Unit.vhd F03x/klessydra-f0-3th/RTL-Processing_Pipeline_TMR.vhd F03x/klessydra-f0-3th/RTL-Program_Counter_unit_TMR.vhd F03x/klessydra-f0-3th/CMP-TMR_REG.vhd F03x/klessydra-f0-3th/STR-Klessydra_top.vhd F03x/klessydra-f0-3th/RTL-Program_Counter_unit_TMR.vhd:129:12:warning: declaration of "taken_branch" hides port "taken_branch" [-Whide] signal taken_branch : in std_logic; ^ F03x/klessydra-f0-3th/RTL-Program_Counter_unit_TMR.vhd:130:12:warning: declaration of "wfi_condition_pending" hides signal "wfi_condition_pending" [-Whide] signal wfi_condition_pending : out std_logic; ^ F03x/klessydra-f0-3th/RTL-Program_Counter_unit_TMR.vhd:131:12:warning: declaration of "set_wfi_condition" hides port "set_wfi_condition" [-Whide] signal set_wfi_condition : in std_logic; ^ F03x/klessydra-f0-3th/RTL-Program_Counter_unit_TMR.vhd:132:12:warning: declaration of "taken_branch_pending" hides port "taken_branch_pending" [-Whide] signal taken_branch_pending : in std_logic; ^ F03x/klessydra-f0-3th/RTL-Program_Counter_unit_TMR.vhd:133:16:warning: declaration of "taken_branch_pending_wire" hides signal "taken_branch_pending_wire" [-Whide] signal taken_branch_pending_wire : out std_logic; ^ F03x/klessydra-f0-3th/RTL-Program_Counter_unit_TMR.vhd:134:12:warning: declaration of "set_except_condition" hides port "set_except_condition" [-Whide] signal set_except_condition : in std_logic; ^ F03x/klessydra-f0-3th/RTL-Program_Counter_unit_TMR.vhd:135:12:warning: declaration of "set_mret_condition" hides port "set_mret_condition" [-Whide] signal set_mret_condition : in std_logic; ^ F03x/klessydra-f0-3th/RTL-Program_Counter_unit_TMR.vhd:136:12:warning: declaration of "pc" hides signal "pc" [-Whide] signal pc : out std_logic_vector(31 downto 0); ^ F03x/klessydra-f0-3th/RTL-Program_Counter_unit_TMR.vhd:137:12:warning: declaration of "taken_branch_pc_lat" hides port "taken_branch_pc_lat" [-Whide] signal taken_branch_pc_lat : in std_logic_vector(31 downto 0); ^ F03x/klessydra-f0-3th/RTL-Program_Counter_unit_TMR.vhd:138:12:warning: declaration of "incremented_pc" hides port "incremented_pc" [-Whide] signal incremented_pc : in std_logic_vector(31 downto 0); ^ F03x/klessydra-f0-3th/RTL-Program_Counter_unit_TMR.vhd:139:12:warning: declaration of "boot_pc" hides signal "boot_pc" [-Whide] signal boot_pc : in std_logic_vector(31 downto 0); ^ F03x/klessydra-f0-3th/RTL-Program_Counter_unit_TMR.vhd:140:12:warning: declaration of "pc_update_enable" hides signal "pc_update_enable" [-Whide] signal pc_update_enable : in std_logic; ^ F03x/klessydra-f0-3th/RTL-Program_Counter_unit_TMR.vhd:141:12:warning: declaration of "served_except_condition" hides port "served_except_condition" [-Whide] signal served_except_condition : out std_logic; ^ F03x/klessydra-f0-3th/RTL-Program_Counter_unit_TMR.vhd:142:12:warning: declaration of "served_mret_condition" hides port "served_mret_condition" [-Whide] signal served_mret_condition : out std_logic) is ^ [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // node [Pipeline] End of Pipeline Finished: SUCCESS