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Start of Pipeline - (5 min 8 sec in block)
node - (5 min 7 sec in block)
node block - (5 min 6 sec in block)
stage - (3.4 sec in block)Git Clone
stage block (Git Clone) - (3 sec in block)
sh - (0.49 sec in self)rm -rf DV-CPU-RV
sh - (2.2 sec in self)git clone --recursive https://github.com/devindang/dv-cpu-rv.git DV-CPU-RV
stage - (2 sec in block)Simulation
stage block (Simulation) - (1.5 sec in block)
dir - (0.96 sec in block)DV-CPU-RV
dir block - (0.69 sec in block)
sh - (0.44 sec in self)iverilog -o simulation.out -g2005 -s rv_core core/rtl/rv_alu.v core/rtl/rv_alu_ctrl.v core/rtl/rv_branch_predict.v core/rtl/rv_branch_test.v core/rtl/rv_core.v core/rtl/rv_ctrl.v core/rtl/rv_data_mem.v core/rtl/rv_div.v core/rtl/rv_dpram.v core/rtl/rv_forward.v core/rtl/rv_hzd_detect.v core/rtl/rv_imm_gen.v core/rtl/rv_instr_mem.v core/rtl/rv_mem_map.v core/rtl/rv_mul.v core/rtl/rv_rf.v && vvp simulation.out
stage - (4 min 59 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (4 min 58 sec in block)
parallel - (4 min 58 sec in block)
parallel block (Branch: colorlight_i9) - (67 ms in block)
stage - (7.9 sec in block)colorlight_i9
stage block (colorlight_i9) - (7.5 sec in block)
lock - (6.6 sec in block)colorlight_i9
lock block - (5.9 sec in block)
stage - (3.1 sec in block)Síntese e PnR
stage block (Síntese e PnR) - (2.4 sec in block)
dir - (1.7 sec in block)DV-CPU-RV
dir block - (1.3 sec in block)
echo - (0.2 sec in self)Iniciando síntese para FPGA colorlight_i9.
sh - (0.74 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p DV-CPU-RV -b colorlight_i9
stage - (1 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (0.38 sec in block)
getContext - (0.16 sec in self)
stage - (0.76 sec in block)Teste colorlight_i9
stage block (Teste colorlight_i9) - (0.43 sec in block)
getContext - (0.19 sec in self)
parallel block (Branch: digilent_nexys4_ddr) - (4 min 57 sec in block)
stage - (4 min 57 sec in block)digilent_nexys4_ddr
stage block (digilent_nexys4_ddr) - (4 min 56 sec in block)
lock - (4 min 55 sec in block)digilent_nexys4_ddr
lock block - (4 min 55 sec in block)
stage - (4 min 39 sec in block)Síntese e PnR
stage block (Síntese e PnR) - (4 min 38 sec in block)
dir - (4 min 37 sec in block)DV-CPU-RV
dir block - (4 min 37 sec in block)
echo - (0.17 sec in self)Iniciando síntese para FPGA digilent_nexys4_ddr.
sh - (4 min 36 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p DV-CPU-RV -b digilent_nexys4_ddr
stage - (14 sec in block)Flash digilent_nexys4_ddr
stage block (Flash digilent_nexys4_ddr) - (13 sec in block)
dir - (13 sec in block)DV-CPU-RV
dir block - (12 sec in block)
echo - (0.16 sec in self)FPGA digilent_nexys4_ddr bloqueada para flash.
sh - (12 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p DV-CPU-RV -b digilent_nexys4_ddr -l
stage - (1.3 sec in block)Teste digilent_nexys4_ddr
stage block (Teste digilent_nexys4_ddr) - (1 sec in block)
echo - (0.23 sec in self)Testando FPGA digilent_nexys4_ddr.
dir - (0.43 sec in block)DV-CPU-RV
dir block - (0.15 sec in block)
stage - (1.6 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (1.3 sec in block)
dir - (0.9 sec in block)DV-CPU-RV
dir block - (0.62 sec in block)
sh - (0.42 sec in self)rm -rf *