Console Output

+ iverilog -o simulation.out -g2005 -s rv_core core/rtl/rv_alu.v core/rtl/rv_alu_ctrl.v core/rtl/rv_branch_predict.v core/rtl/rv_core.v core/rtl/rv_ctrl.v core/rtl/rv_data_mem.v core/rtl/rv_div.v core/rtl/rv_dpram.v core/rtl/rv_forward.v core/rtl/rv_hzd_detect.v core/rtl/rv_imm_gen.v core/rtl/rv_instr_mem.v core/rtl/rv_mem_map.v core/rtl/rv_mul.v core/rtl/rv_rf.v
core/rtl/rv_core.v:366: error: Unknown module type: rv_branch_test
2 error(s) during elaboration.
*** These modules were missing:
        rv_branch_test referenced 1 times.
***