Console Output

+ iverilog -o simulation.out -g2005 -s tb_rv_core rtl/rv_alu_ctrl.v rtl/rv_alu.v rtl/rv_branch_predict.v rtl/rv_branch_test.v rtl/rv_core.v rtl/rv_ctrl.v rtl/rv_data_mem.v rtl/rv_div.v rtl/rv_dpram.v rtl/rv_forward.v rtl/rv_hzd_detect.v rtl/rv_imm_gen.v rtl/rv_instr_mem.v rtl/rv_mem_map.v rtl/rv_mul.v rtl/rv_rf.v bench/tb_rv_core.v
rtl/rv_alu_ctrl.v: No such file or directory
error: Unable to find the root module "tb_rv_core" in the Verilog source.
     : Perhaps ``-s tb_rv_core'' is incorrect?
1 error(s) during elaboration.