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Start of Pipeline - (18 sec in block)
node - (17 sec in block)
node block - (16 sec in block)
stage - (4 sec in block)Git Clone
stage block (Git Clone) - (3.5 sec in block)
sh - (0.45 sec in self)rm -rf DV-CPU-RV
sh - (2.8 sec in self)git clone --recursive https://github.com/devindang/dv-cpu-rv.git DV-CPU-RV
stage - (2 sec in block)Simulation
stage block (Simulation) - (1.5 sec in block)
dir - (1 sec in block)DV-CPU-RV
dir block - (0.74 sec in block)
sh - (0.51 sec in self)iverilog -o simulation.out -g2005 -s tb_rv_core rtl/rv_alu_ctrl.v rtl/rv_alu.v rtl/rv_branch_predict.v rtl/rv_branch_test.v rtl/rv_core.v rtl/rv_ctrl.v rtl/rv_data_mem.v rtl/rv_div.v rtl/rv_dpram.v rtl/rv_forward.v rtl/rv_hzd_detect.v rtl/rv_imm_gen.v rtl/rv_instr_mem.v rtl/rv_mem_map.v rtl/rv_mul.v rtl/rv_rf.v bench/tb_rv_core.v && vvp simulation.out
stage - (9.1 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (8.4 sec in block)
getContext - (0.28 sec in self)
parallel - (7.8 sec in block)
parallel block (Branch: colorlight_i9) - (56 ms in block)
stage - (6.4 sec in block)colorlight_i9
stage block (colorlight_i9) - (5.9 sec in block)
getContext - (0.63 sec in self)
stage - (1.6 sec in block)Síntese e PnR
stage block (Síntese e PnR) - (0.53 sec in block)
getContext - (0.16 sec in self)
stage - (1.6 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (0.6 sec in block)
getContext - (0.16 sec in self)
stage - (1.2 sec in block)Teste colorlight_i9
stage block (Teste colorlight_i9) - (0.6 sec in block)
getContext - (0.16 sec in self)
parallel block (Branch: digilent_nexys4_ddr) - (7.1 sec in block)
stage - (6.3 sec in block)digilent_nexys4_ddr
stage block (digilent_nexys4_ddr) - (5.8 sec in block)
getContext - (0.59 sec in self)
stage - (1.6 sec in block)Síntese e PnR
stage block (Síntese e PnR) - (0.68 sec in block)
getContext - (0.16 sec in self)
stage - (1.6 sec in block)Flash digilent_nexys4_ddr
stage block (Flash digilent_nexys4_ddr) - (0.71 sec in block)
getContext - (0.16 sec in self)
stage - (1.2 sec in block)Teste digilent_nexys4_ddr
stage block (Teste digilent_nexys4_ddr) - (0.7 sec in block)
getContext - (0.15 sec in self)
stage - (1.4 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (1.2 sec in block)
dir - (0.83 sec in block)DV-CPU-RV
dir block - (0.6 sec in block)
sh - (0.4 sec in self)rm -rf *