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| Step | Arguments | Status | ||
|---|---|---|---|---|
| Start of Pipeline - (7 sec in block) | ||||
| node - (6.4 sec in block) | ||||
| node block - (6 sec in block) | ||||
| stage - (3.9 sec in block) | git_clone | |||
| stage block (git_clone) - (3.5 sec in block) | ||||
| sh - (0.46 sec in self) | rm -Rf dv-cpu-rv/ build/ | |||
| sh - (2.8 sec in self) | git clone https://github.com/devindang/dv-cpu-rv.git | |||
| stage - (1.6 sec in block) | Yosys | |||
| stage block (Yosys) - (1.2 sec in block) | ||||
| dir - (0.84 sec in block) | dv-cpu-rv/core/ | |||
| dir block - (0.6 sec in block) | ||||
| sh - (0.4 sec in self) | /usr/bin/iverilog -o test.o -s tb_rv_core bench/tb_rv_core.v rtl/rv_alu_ctrl.v rtl/rv_alu.v rtl/rv_branch_predict.v rtl/rv_branch_test.v rtl/rv_core.v rtl/rv_ctrl.v rtl/rv_data_mem.v rtl/rv_div.v rtl/rv_dpram.v rtl/rv_forward.v rtl/rv_hzd_detect.v rtl/rv_imm_gen.v rtl/rv_instr_mem.v rtl/rv_mem_map.v rtl/rv_mul.v rtl/rv_rf.v |