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+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p Cores-VeeR-EL2 -b digilent_arty_a7_100t
Final configuration file generated at /var/jenkins_home/workspace/Cores-VeeR-EL2/Cores-VeeR-EL2/build_digilent_arty_a7_100t.tcl
Error executing Makefile.
ERROR: [Synth 8-9263] cannot open include file 'el2_param.vh' [/var/jenkins_home/workspace/Cores-VeeR-EL2/Cores-VeeR-EL2/design/el2_dma_ctrl.sv:27]
ERROR: [Synth 8-9263] cannot open include file 'el2_param.vh' [/var/jenkins_home/workspace/Cores-VeeR-EL2/Cores-VeeR-EL2/design/el2_mem.sv:22]
ERROR: [Synth 8-9263] cannot open include file 'el2_param.vh' [/var/jenkins_home/workspace/Cores-VeeR-EL2/Cores-VeeR-EL2/design/el2_pic_ctrl.sv:26]
ERROR: [Synth 8-9263] cannot open include file 'pic_map_auto.h' [/var/jenkins_home/workspace/Cores-VeeR-EL2/Cores-VeeR-EL2/design/el2_pic_ctrl.sv:536]
ERROR: [Synth 8-9263] cannot open include file 'el2_param.vh' [/var/jenkins_home/workspace/Cores-VeeR-EL2/Cores-VeeR-EL2/design/el2_pmp.sv:24]
ERROR: [Synth 8-9263] cannot open include file 'el2_param.vh' [/var/jenkins_home/workspace/Cores-VeeR-EL2/Cores-VeeR-EL2/design/el2_veer.sv:26]
ERROR: [Synth 8-9263] cannot open include file 'el2_param.vh' [/var/jenkins_home/workspace/Cores-VeeR-EL2/Cores-VeeR-EL2/design/dbg/el2_dbg.sv:27]
ERROR: [Synth 8-9263] cannot open include file 'el2_param.vh' [/var/jenkins_home/workspace/Cores-VeeR-EL2/Cores-VeeR-EL2/design/dec/el2_dec.sv:33]
ERROR: [Synth 8-9263] cannot open include file 'el2_param.vh' [/var/jenkins_home/workspace/Cores-VeeR-EL2/Cores-VeeR-EL2/design/dec/el2_dec_decode_ctl.sv:20]
ERROR: [Synth 8-9263] cannot open include file 'el2_param.vh' [/var/jenkins_home/workspace/Cores-VeeR-EL2/Cores-VeeR-EL2/design/dec/el2_dec_gpr_ctl.sv:19]
ERROR: [Synth 8-9263] cannot open include file 'el2_param.vh' [/var/jenkins_home/workspace/Cores-VeeR-EL2/Cores-VeeR-EL2/design/dec/el2_dec_ib_ctl.sv:19]
ERROR: [Synth 8-9263] cannot open include file 'el2_param.vh' [/var/jenkins_home/workspace/Cores-VeeR-EL2/Cores-VeeR-EL2/design/dec/el2_dec_pmp_ctl.sv:29]
ERROR: [Synth 8-9263] cannot open include file 'el2_param.vh' [/var/jenkins_home/workspace/Cores-VeeR-EL2/Cores-VeeR-EL2/design/dec/el2_dec_tlu_ctl.sv:29]
ERROR: [Synth 8-9263] cannot open include file 'el2_dec_csr_equ_m.svh' [/var/jenkins_home/workspace/Cores-VeeR-EL2/Cores-VeeR-EL2/design/dec/el2_dec_tlu_ctl.sv:504]
ERROR: [Synth 8-9263] cannot open include file 'el2_param.vh' [/var/jenkins_home/workspace/Cores-VeeR-EL2/Cores-VeeR-EL2/design/dec/el2_dec_tlu_ctl.sv:3052]
ERROR: [Synth 8-9263] cannot open include file 'el2_param.vh' [/var/jenkins_home/workspace/Cores-VeeR-EL2/Cores-VeeR-EL2/design/dec/el2_dec_trigger.sv:28]
ERROR: [Synth 8-9263] cannot open include file 'el2_param.vh' [/var/jenkins_home/workspace/Cores-VeeR-EL2/Cores-VeeR-EL2/design/exu/el2_exu.sv:20]
ERROR: [Synth 8-9263] cannot open include file 'el2_param.vh' [/var/jenkins_home/workspace/Cores-VeeR-EL2/Cores-VeeR-EL2/design/exu/el2_exu_alu_ctl.sv:20]
ERROR: [Synth 8-9263] cannot open include file 'el2_param.vh' [/var/jenkins_home/workspace/Cores-VeeR-EL2/Cores-VeeR-EL2/design/exu/el2_exu_div_ctl.sv:20]
ERROR: [Synth 8-9263] cannot open include file 'el2_pdef.vh' [/var/jenkins_home/workspace/Cores-VeeR-EL2/Cores-VeeR-EL2/design/include/el2_def.sv:6]
ERROR: [Synth 8-439] module 'processorci_top' not found
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
make: *** [/eda/processor_ci/makefiles/digilent_arty_a7_100t.mk:12: digilent_arty_a7_100t.bit] Error 1

Traceback (most recent call last):
  File "/eda/processor_ci/main.py", line 135, in <module>
    main(
  File "/eda/processor_ci/main.py", line 82, in main
    build(build_file_path, board_name, toolchain_path)
  File "/eda/processor_ci/core/fpga.py", line 307, in build
    raise subprocess.CalledProcessError(process.returncode, 'make')
subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2.