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Started by timer
[Pipeline] Start of Pipeline
[Pipeline] node
Running on Jenkins in /var/jenkins_home/workspace/Cores-VeeR-EL2
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone)
[Pipeline] sh
+ rm -rf Cores-VeeR-EL2
[Pipeline] sh
+ git clone --recursive --depth=1 https://github.com/chipsalliance/Cores-VeeR-EL2 Cores-VeeR-EL2
Cloning into 'Cores-VeeR-EL2'...
Submodule 'third_party/cocotb' (https://github.com/cocotb/cocotb) registered for path 'third_party/cocotb'
Submodule 'third-party/picolibc' (https://github.com/picolibc/picolibc) registered for path 'third_party/picolibc'
Submodule 'third_party/riscv-dv' (https://github.com/chipsalliance/riscv-dv) registered for path 'third_party/riscv-dv'
Cloning into '/var/jenkins_home/workspace/Cores-VeeR-EL2/Cores-VeeR-EL2/third_party/cocotb'...
Cloning into '/var/jenkins_home/workspace/Cores-VeeR-EL2/Cores-VeeR-EL2/third_party/picolibc'...
Cloning into '/var/jenkins_home/workspace/Cores-VeeR-EL2/Cores-VeeR-EL2/third_party/riscv-dv'...
Submodule path 'third_party/cocotb': checked out '7789fdf57ac1d509631c7f8eeb63cf455562bb96'
Submodule path 'third_party/picolibc': checked out '0694a78fc08b3300c7db79602c46ba0a64428c8e'
Submodule path 'third_party/riscv-dv': checked out '7e54b678ab7499040336255550cdbd99ae887431'
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Simulation)
[Pipeline] dir
Running in /var/jenkins_home/workspace/Cores-VeeR-EL2/Cores-VeeR-EL2
[Pipeline] {
[Pipeline] echo
simulation not supported for System Verilog files
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Utilities)
[Pipeline] dir
Running in /var/jenkins_home/workspace/Cores-VeeR-EL2/Cores-VeeR-EL2
[Pipeline] {
[Pipeline] sh
+ pwd
+ python3 /eda/processor_ci/core/labeler_prototype.py -d /var/jenkins_home/workspace/Cores-VeeR-EL2/Cores-VeeR-EL2 -c /eda/processor_ci/config.json -o /jenkins/processor_ci_utils/labels
Trying to read file: /var/jenkins_home/workspace/Cores-VeeR-EL2/Cores-VeeR-EL2/design/el2_veer.sv
Cache-related signals in el2_veer_lockstep_wrapper.sv
Cache-related signals in el2_exu_div_ctl_wrapper.sv
Cache-related signals in el2_ifu_mem_ctl_wrapper.sv
Cache-related signals in el2_lsu_trigger_wrapper.sv
Cache-related signals in el2_tlu_ctl_wrapper.sv
Cache-related signals in el2_dec_wrapper.sv
Cache-related signals in el2_dec_ib_ctl_wrapper.sv
Cache-related signals in el2_exu_mul_ctl_wrapper.sv
Cache-related signals in riscv_illegal_instr.sv
Cache-related signals in riscv_instr_sequence.sv
Cache-related signals in riscv_pmp_cfg.sv
Cache-related signals in riscv_page_table_entry.sv
Cache-related signals in riscv_reg.sv
Cache-related signals in riscv_asm_program_gen.sv
Cache-related signals in riscv_page_table_list.sv
Cache-related signals in riscv_compressed_instr.sv
Cache-related signals in riscv_instr.sv
Cache-related signals in uart_parser.v
Cache-related signals in analog_probe_cadence.sv
Cache-related signals in el2_veer_lockstep.sv
Cache-related signals in el2_dma_ctrl.sv
Cache-related signals in el2_mem.sv
Cache-related signals in el2_veer_wrapper.sv
Cache-related signals in el2_veer.sv
Cache-related signals in axi4_to_ahb.sv
Cache-related signals in el2_mem_if.sv
Cache-related signals in ahb_to_axi4.sv
Cache-related signals in el2_lsu_bus_buffer.sv
Cache-related signals in el2_lsu_trigger.sv
Cache-related signals in el2_lsu_addrcheck.sv
Cache-related signals in el2_lsu_stbuf.sv
Cache-related signals in el2_lsu_clkdomain.sv
Cache-related signals in el2_lsu_lsc_ctl.sv
Cache-related signals in el2_lsu_dccm_ctl.sv
Cache-related signals in el2_lsu_ecc.sv
Cache-related signals in el2_lsu_bus_intf.sv
Cache-related signals in el2_lsu.sv
Cache-related signals in el2_dec.sv
Cache-related signals in el2_dec_decode_ctl.sv
Cache-related signals in el2_dec_tlu_ctl.sv
Cache-related signals in el2_dec_ib_ctl.sv
Cache-related signals in el2_dbg.sv
Cache-related signals in el2_def.sv
Cache-related signals in el2_ifu_ic_mem.sv
Cache-related signals in el2_ifu_ifc_ctl.sv
Cache-related signals in el2_ifu_iccm_mem.sv
Cache-related signals in el2_ifu_aln_ctl.sv
Cache-related signals in el2_ifu_bp_ctl.sv
Cache-related signals in el2_ifu_mem_ctl.sv
Cache-related signals in el2_ifu.sv
Cache-related signals in el2_exu.sv
Cache-related signals in el2_exu_div_ctl.sv
Cache-related signals in el2_exu_mul_ctl.sv
Cache-related signals in axi_register_wr.v
Cache-related signals in axi_register_rd.v
Cache-related signals in priority_encoder.v
Results saved to /jenkins/processor_ci_utils/labels/Cores-VeeR-EL2.json
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Build Pipeline)
[Pipeline] parallel
[Pipeline] { (Branch: colorlight_i9)
[Pipeline] { (Branch: digilent_arty_a7_100t)
[Pipeline] stage
[Pipeline] { (colorlight_i9)
[Pipeline] stage
[Pipeline] { (digilent_arty_a7_100t)
[Pipeline] lock
Trying to acquire lock on [Resource: colorlight_i9]
The resource [colorlight_i9] is locked by build biriscv #184 #184 since Apr 5, 2025, 3:12 AM.
[Resource: colorlight_i9] is not free, waiting for execution ...
[Required resources: [colorlight_i9]] added into queue at position 0
[Pipeline] lock
Trying to acquire lock on [Resource: digilent_arty_a7_100t]
The resource [digilent_arty_a7_100t] is locked by build biriscv #184 #184 since Apr 5, 2025, 3:16 AM.
[Resource: digilent_arty_a7_100t] is not free, waiting for execution ...
[Required resources: [digilent_arty_a7_100t]] added into queue at position 1
Lock acquired on [Resource: digilent_arty_a7_100t]
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Synthesis and PnR)
[Pipeline] dir
Running in /var/jenkins_home/workspace/Cores-VeeR-EL2/Cores-VeeR-EL2
[Pipeline] {
[Pipeline] echo
Starting synthesis for FPGA digilent_arty_a7_100t.
[Pipeline] sh
+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p Cores-VeeR-EL2 -b digilent_arty_a7_100t
Final configuration file generated at /var/jenkins_home/workspace/Cores-VeeR-EL2/Cores-VeeR-EL2/build_digilent_arty_a7_100t.tcl
Error executing Makefile.
ERROR: [Synth 8-9263] cannot open include file 'el2_param.vh' [/var/jenkins_home/workspace/Cores-VeeR-EL2/Cores-VeeR-EL2/design/el2_dma_ctrl.sv:27]
ERROR: [Synth 8-9263] cannot open include file 'el2_param.vh' [/var/jenkins_home/workspace/Cores-VeeR-EL2/Cores-VeeR-EL2/design/el2_mem.sv:22]
ERROR: [Synth 8-9263] cannot open include file 'el2_param.vh' [/var/jenkins_home/workspace/Cores-VeeR-EL2/Cores-VeeR-EL2/design/el2_pic_ctrl.sv:26]
ERROR: [Synth 8-9263] cannot open include file 'pic_map_auto.h' [/var/jenkins_home/workspace/Cores-VeeR-EL2/Cores-VeeR-EL2/design/el2_pic_ctrl.sv:536]
ERROR: [Synth 8-9263] cannot open include file 'el2_param.vh' [/var/jenkins_home/workspace/Cores-VeeR-EL2/Cores-VeeR-EL2/design/el2_pmp.sv:24]
ERROR: [Synth 8-9263] cannot open include file 'el2_param.vh' [/var/jenkins_home/workspace/Cores-VeeR-EL2/Cores-VeeR-EL2/design/el2_veer.sv:26]
ERROR: [Synth 8-9263] cannot open include file 'el2_param.vh' [/var/jenkins_home/workspace/Cores-VeeR-EL2/Cores-VeeR-EL2/design/dbg/el2_dbg.sv:27]
ERROR: [Synth 8-9263] cannot open include file 'el2_param.vh' [/var/jenkins_home/workspace/Cores-VeeR-EL2/Cores-VeeR-EL2/design/dec/el2_dec.sv:33]
ERROR: [Synth 8-9263] cannot open include file 'el2_param.vh' [/var/jenkins_home/workspace/Cores-VeeR-EL2/Cores-VeeR-EL2/design/dec/el2_dec_decode_ctl.sv:20]
ERROR: [Synth 8-9263] cannot open include file 'el2_param.vh' [/var/jenkins_home/workspace/Cores-VeeR-EL2/Cores-VeeR-EL2/design/dec/el2_dec_gpr_ctl.sv:19]
ERROR: [Synth 8-9263] cannot open include file 'el2_param.vh' [/var/jenkins_home/workspace/Cores-VeeR-EL2/Cores-VeeR-EL2/design/dec/el2_dec_ib_ctl.sv:19]
ERROR: [Synth 8-9263] cannot open include file 'el2_param.vh' [/var/jenkins_home/workspace/Cores-VeeR-EL2/Cores-VeeR-EL2/design/dec/el2_dec_pmp_ctl.sv:29]
ERROR: [Synth 8-9263] cannot open include file 'el2_param.vh' [/var/jenkins_home/workspace/Cores-VeeR-EL2/Cores-VeeR-EL2/design/dec/el2_dec_tlu_ctl.sv:29]
ERROR: [Synth 8-9263] cannot open include file 'el2_dec_csr_equ_m.svh' [/var/jenkins_home/workspace/Cores-VeeR-EL2/Cores-VeeR-EL2/design/dec/el2_dec_tlu_ctl.sv:504]
ERROR: [Synth 8-9263] cannot open include file 'el2_param.vh' [/var/jenkins_home/workspace/Cores-VeeR-EL2/Cores-VeeR-EL2/design/dec/el2_dec_tlu_ctl.sv:3052]
ERROR: [Synth 8-9263] cannot open include file 'el2_param.vh' [/var/jenkins_home/workspace/Cores-VeeR-EL2/Cores-VeeR-EL2/design/dec/el2_dec_trigger.sv:28]
ERROR: [Synth 8-9263] cannot open include file 'el2_param.vh' [/var/jenkins_home/workspace/Cores-VeeR-EL2/Cores-VeeR-EL2/design/exu/el2_exu.sv:20]
ERROR: [Synth 8-9263] cannot open include file 'el2_param.vh' [/var/jenkins_home/workspace/Cores-VeeR-EL2/Cores-VeeR-EL2/design/exu/el2_exu_alu_ctl.sv:20]
ERROR: [Synth 8-9263] cannot open include file 'el2_param.vh' [/var/jenkins_home/workspace/Cores-VeeR-EL2/Cores-VeeR-EL2/design/exu/el2_exu_div_ctl.sv:20]
ERROR: [Synth 8-9263] cannot open include file 'el2_pdef.vh' [/var/jenkins_home/workspace/Cores-VeeR-EL2/Cores-VeeR-EL2/design/include/el2_def.sv:6]
ERROR: [Synth 8-439] module 'processorci_top' not found
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
make: *** [/eda/processor_ci/makefiles/digilent_arty_a7_100t.mk:12: digilent_arty_a7_100t.bit] Error 1

Traceback (most recent call last):
  File "/eda/processor_ci/main.py", line 135, in <module>
    main(
  File "/eda/processor_ci/main.py", line 82, in main
    build(build_file_path, board_name, toolchain_path)
  File "/eda/processor_ci/core/fpga.py", line 307, in build
    raise subprocess.CalledProcessError(process.returncode, 'make')
subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2.
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash digilent_arty_a7_100t)
Stage "Flash digilent_arty_a7_100t" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Test digilent_arty_a7_100t)
Stage "Test digilent_arty_a7_100t" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Lock released on resource [Resource: digilent_arty_a7_100t]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Failed in branch digilent_arty_a7_100t
Lock acquired on [Resource: colorlight_i9]
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Synthesis and PnR)
[Pipeline] dir
Running in /var/jenkins_home/workspace/Cores-VeeR-EL2/Cores-VeeR-EL2
[Pipeline] {
[Pipeline] echo
Starting synthesis for FPGA colorlight_i9.
[Pipeline] sh
+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p Cores-VeeR-EL2 -b colorlight_i9
Final configuration file generated at /var/jenkins_home/workspace/Cores-VeeR-EL2/Cores-VeeR-EL2/build_colorlight_i9.tcl
Error executing Makefile.
/var/jenkins_home/workspace/Cores-VeeR-EL2/Cores-VeeR-EL2/design/dmi/dmi_mux.v:32: ERROR: syntax error, unexpected ';', expecting '(' or '['
make: *** [/eda/processor_ci/makefiles/colorlight_i9.mk:12: colorlight_i9.json] Error 1

Traceback (most recent call last):
  File "/eda/processor_ci/main.py", line 135, in <module>
    main(
  File "/eda/processor_ci/main.py", line 82, in main
    build(build_file_path, board_name, toolchain_path)
  File "/eda/processor_ci/core/fpga.py", line 307, in build
    raise subprocess.CalledProcessError(process.returncode, 'make')
subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2.
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash colorlight_i9)
Stage "Flash colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Test colorlight_i9)
Stage "Test colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Lock released on resource [Resource: colorlight_i9]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Failed in branch colorlight_i9
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Declarative: Post Actions)
[Pipeline] junit
Recording test results
No test report files were found. Configuration error?
Error when executing always post condition:
Also:   org.jenkinsci.plugins.workflow.actions.ErrorAction$ErrorId: 59402ebb-81f9-456b-a13e-7ee1d9ae7fb5
hudson.AbortException: No test report files were found. Configuration error?
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser$ParseResultCallable.invoke(JUnitParser.java:253)
	at hudson.FilePath.act(FilePath.java:1234)
	at hudson.FilePath.act(FilePath.java:1217)
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser.parseResult(JUnitParser.java:146)
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parse(JUnitResultArchiver.java:177)
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parseAndSummarize(JUnitResultArchiver.java:282)
	at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:62)
	at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:27)
	at PluginClassLoader for workflow-step-api//org.jenkinsci.plugins.workflow.steps.SynchronousNonBlockingStepExecution.lambda$start$0(SynchronousNonBlockingStepExecution.java:49)
	at java.base/java.util.concurrent.Executors$RunnableAdapter.call(Unknown Source)
	at java.base/java.util.concurrent.FutureTask.run(Unknown Source)
	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(Unknown Source)
	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(Unknown Source)
	at java.base/java.lang.Thread.run(Unknown Source)

[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
ERROR: script returned exit code 1
Finished: FAILURE