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Start of Pipeline - (43 min in block)
node - (43 min in block)
node block - (43 min in block)
stage - (43 sec in block)Git Clone
stage block (Git Clone) - (42 sec in block)
sh - (0.5 sec in self)rm -rf Cores-VeeR-EL2
sh - (42 sec in self)git clone --recursive --depth=1 https://github.com/chipsalliance/Cores-VeeR-EL2 Cores-VeeR-EL2
stage - (1.4 sec in block)Simulation
stage block (Simulation) - (0.98 sec in block)
dir - (0.59 sec in block)Cores-VeeR-EL2
dir block - (0.31 sec in block)
echo - (0.1 sec in self)simulation not supported for System Verilog files
stage - (1.9 sec in block)Utilities
stage block (Utilities) - (1.4 sec in block)
dir - (1.1 sec in block)Cores-VeeR-EL2
dir block - (0.86 sec in block)
sh - (0.66 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config.json -o /jenkins/processor_ci_utils/labels
stage - (42 min in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (42 min in block)
parallel - (42 min in block)
parallel block (Branch: colorlight_i9) - (66 ms in block)
stage - (42 min in block)colorlight_i9
stage block (colorlight_i9) - (42 min in block)
lock - (42 min in block)colorlight_i9
lock block - (7.8 sec in block)
stage - (4 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (2.9 sec in block)
dir - (2.1 sec in block)Cores-VeeR-EL2
dir block - (1.4 sec in block)
echo - (0.34 sec in self)Starting synthesis for FPGA colorlight_i9.
sh - (0.64 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p Cores-VeeR-EL2 -b colorlight_i9
stage - (2.1 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (0.77 sec in block)
getContext - (0.33 sec in self)
stage - (1 sec in block)Test colorlight_i9
stage block (Test colorlight_i9) - (0.62 sec in block)
getContext - (0.22 sec in self)
parallel block (Branch: digilent_arty_a7_100t) - (41 min in block)
stage - (41 min in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (41 min in block)
lock - (41 min in block)digilent_arty_a7_100t
lock block - (1 min 12 sec in block)
stage - (1 min 10 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (1 min 9 sec in block)
dir - (1 min 8 sec in block)Cores-VeeR-EL2
dir block - (1 min 8 sec in block)
echo - (0.15 sec in self)Starting synthesis for FPGA digilent_arty_a7_100t.
sh - (1 min 8 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p Cores-VeeR-EL2 -b digilent_arty_a7_100t
stage - (0.96 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (0.37 sec in block)
getContext - (0.16 sec in self)
stage - (0.67 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (0.38 sec in block)
getContext - (0.17 sec in self)
stage - (0.74 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.52 sec in block)
junit - (0.28 sec in self)**/test-reports/*.xml