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+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p Cores-VeeR-EH2 -b digilent_arty_a7_100t
Final configuration file generated at /var/jenkins_home/workspace/Cores-VeeR-EH2/Cores-VeeR-EH2/build_digilent_arty_a7_100t.tcl
Error executing Makefile.
ERROR: [Synth 8-9263] cannot open include file 'eh2_param.vh' [/var/jenkins_home/workspace/Cores-VeeR-EH2/Cores-VeeR-EH2/design/eh2_dma_ctrl.sv:27]
ERROR: [Synth 8-9263] cannot open include file 'eh2_param.vh' [/var/jenkins_home/workspace/Cores-VeeR-EH2/Cores-VeeR-EH2/design/eh2_pic_ctrl.sv:26]
ERROR: [Synth 8-9263] cannot open include file 'pic_map_auto.h' [/var/jenkins_home/workspace/Cores-VeeR-EH2/Cores-VeeR-EH2/design/eh2_pic_ctrl.sv:673]
ERROR: [Synth 8-9263] cannot open include file 'eh2_param.vh' [/var/jenkins_home/workspace/Cores-VeeR-EH2/Cores-VeeR-EH2/design/eh2_veer.sv:26]
ERROR: [Synth 8-9263] cannot open include file 'eh2_param.vh' [/var/jenkins_home/workspace/Cores-VeeR-EH2/Cores-VeeR-EH2/design/dbg/eh2_dbg.sv:25]
ERROR: [Synth 8-9263] cannot open include file 'eh2_param.vh' [/var/jenkins_home/workspace/Cores-VeeR-EH2/Cores-VeeR-EH2/design/dec/eh2_dec.sv:30]
ERROR: [Synth 8-9263] cannot open include file 'eh2_param.vh' [/var/jenkins_home/workspace/Cores-VeeR-EH2/Cores-VeeR-EH2/design/dec/eh2_dec_csr.sv:28]
ERROR: [Synth 8-9263] cannot open include file 'eh2_param.vh' [/var/jenkins_home/workspace/Cores-VeeR-EH2/Cores-VeeR-EH2/design/dec/eh2_dec_decode_ctl.sv:20]
ERROR: [Synth 8-9263] cannot open include file 'eh2_param.vh' [/var/jenkins_home/workspace/Cores-VeeR-EH2/Cores-VeeR-EH2/design/dec/eh2_dec_decode_ctl.sv:3179]
ERROR: [Synth 8-9263] cannot open include file 'eh2_param.vh' [/var/jenkins_home/workspace/Cores-VeeR-EH2/Cores-VeeR-EH2/design/dec/eh2_dec_gpr_ctl.sv:19]
ERROR: [Synth 8-9263] cannot open include file 'eh2_param.vh' [/var/jenkins_home/workspace/Cores-VeeR-EH2/Cores-VeeR-EH2/design/dec/eh2_dec_ib_ctl.sv:19]
ERROR: [Synth 8-9263] cannot open include file 'eh2_param.vh' [/var/jenkins_home/workspace/Cores-VeeR-EH2/Cores-VeeR-EH2/design/dec/eh2_dec_tlu_ctl.sv:29]
ERROR: [Synth 8-9263] cannot open include file 'eh2_param.vh' [/var/jenkins_home/workspace/Cores-VeeR-EH2/Cores-VeeR-EH2/design/dec/eh2_dec_tlu_ctl.sv:2355]
ERROR: [Synth 8-9263] cannot open include file 'eh2_param.vh' [/var/jenkins_home/workspace/Cores-VeeR-EH2/Cores-VeeR-EH2/design/dec/eh2_dec_tlu_top.sv:29]
ERROR: [Synth 8-9263] cannot open include file 'eh2_param.vh' [/var/jenkins_home/workspace/Cores-VeeR-EH2/Cores-VeeR-EH2/design/dec/eh2_dec_trigger.sv:28]
ERROR: [Synth 8-9263] cannot open include file 'eh2_param.vh' [/var/jenkins_home/workspace/Cores-VeeR-EH2/Cores-VeeR-EH2/design/exu/eh2_exu.sv:20]
ERROR: [Synth 8-9263] cannot open include file 'eh2_param.vh' [/var/jenkins_home/workspace/Cores-VeeR-EH2/Cores-VeeR-EH2/design/exu/eh2_exu_alu_ctl.sv:20]
ERROR: [Synth 8-9263] cannot open include file 'eh2_param.vh' [/var/jenkins_home/workspace/Cores-VeeR-EH2/Cores-VeeR-EH2/design/exu/eh2_exu_div_ctl.sv:20]
ERROR: [Synth 8-9263] cannot open include file 'eh2_param.vh' [/var/jenkins_home/workspace/Cores-VeeR-EH2/Cores-VeeR-EH2/design/exu/eh2_exu_mul_ctl.sv:20]
ERROR: [Synth 8-9263] cannot open include file 'eh2_param.vh' [/var/jenkins_home/workspace/Cores-VeeR-EH2/Cores-VeeR-EH2/design/eh2_dma_ctrl.sv:27]
ERROR: [Synth 8-439] module 'processorci_top' not found
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
make: *** [/eda/processor_ci/makefiles/digilent_arty_a7_100t.mk:12: digilent_arty_a7_100t.bit] Error 1

Traceback (most recent call last):
  File "/eda/processor_ci/main.py", line 135, in <module>
    main(
  File "/eda/processor_ci/main.py", line 82, in main
    build(build_file_path, board_name, toolchain_path)
  File "/eda/processor_ci/core/fpga.py", line 307, in build
    raise subprocess.CalledProcessError(process.returncode, 'make')
subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2.