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Start of Pipeline - (13 min in block)
node - (13 min in block)
node block - (2 min 26 sec in block)
stage - (2.7 sec in block)Git Clone
stage block (Git Clone) - (2.2 sec in block)
sh - (0.57 sec in self)rm -rf Cores-VeeR-EH2
sh - (1.2 sec in self)git clone --recursive --depth=1 https://github.com/chipsalliance/Cores-VeeR-EH2 Cores-VeeR-EH2
stage - (1.4 sec in block)Simulation
stage block (Simulation) - (0.96 sec in block)
dir - (0.58 sec in block)Cores-VeeR-EH2
dir block - (0.32 sec in block)
echo - (0.1 sec in self)simulation not supported for System Verilog files
stage - (1.7 sec in block)Utilities
stage block (Utilities) - (1.2 sec in block)
dir - (0.85 sec in block)Cores-VeeR-EH2
dir block - (0.59 sec in block)
sh - (0.39 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config.json -o /jenkins/processor_ci_utils/labels
stage - (2 min 19 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (2 min 18 sec in block)
parallel - (2 min 18 sec in block)
parallel block (Branch: colorlight_i9) - (50 ms in block)
stage - (6.1 sec in block)colorlight_i9
stage block (colorlight_i9) - (5.8 sec in block)
lock - (5 sec in block)colorlight_i9
lock block - (4.4 sec in block)
stage - (2.1 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (1.5 sec in block)
dir - (1 sec in block)Cores-VeeR-EH2
dir block - (0.79 sec in block)
echo - (0.17 sec in self)Starting synthesis for FPGA colorlight_i9.
sh - (0.45 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p Cores-VeeR-EH2 -b colorlight_i9
stage - (0.92 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (0.38 sec in block)
getContext - (0.17 sec in self)
stage - (0.66 sec in block)Test colorlight_i9
stage block (Test colorlight_i9) - (0.36 sec in block)
getContext - (0.15 sec in self)
parallel block (Branch: digilent_arty_a7_100t) - (2 min 17 sec in block)
stage - (2 min 16 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (2 min 16 sec in block)
lock - (2 min 14 sec in block)digilent_arty_a7_100t
lock block - (1 min 12 sec in block)
stage - (1 min 10 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (1 min 9 sec in block)
dir - (1 min 9 sec in block)Cores-VeeR-EH2
dir block - (1 min 8 sec in block)
echo - (0.32 sec in self)Starting synthesis for FPGA digilent_arty_a7_100t.
sh - (1 min 8 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p Cores-VeeR-EH2 -b digilent_arty_a7_100t
stage - (1 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (0.41 sec in block)
getContext - (0.2 sec in self)
stage - (0.7 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (0.38 sec in block)
getContext - (0.16 sec in self)
stage - (0.76 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.51 sec in block)
junit - (0.25 sec in self)**/test-reports/*.xml