Skip to content
[Jenkins]Jenkins
log in
StepArgumentsStatus
Start of Pipeline - (56 sec in block)
node - (55 sec in block)
node block - (54 sec in block)
stage - (2.8 sec in block)Git Clone
stage block (Git Clone) - (2.4 sec in block)
sh - (0.47 sec in self)rm -rf *.xml
sh - (0.46 sec in self)rm -rf Cores-VeeR-EH1
sh - (1.2 sec in self)git clone --recursive --depth=1 https://github.com/chipsalliance/Cores-VeeR-EH1 Cores-VeeR-EH1
stage - (1.6 sec in block)Verilog Convert
stage block (Verilog Convert) - (1.2 sec in block)
dir - (0.86 sec in block)Cores-VeeR-EH1
dir block - (0.61 sec in block)
sh - (0.41 sec in self)RV_ROOT=$(pwd) configs/veer.config -set=fpga_optimize=1 -target=default -set=btb_size=128
stage - (1.3 sec in block)Simulation
stage block (Simulation) - (0.92 sec in block)
dir - (0.55 sec in block)Cores-VeeR-EH1
dir block - (0.3 sec in block)
echo - (0.11 sec in self)simulation not supported for System Verilog files
stage - (1.8 sec in block)Utilities
stage block (Utilities) - (1.2 sec in block)
dir - (0.88 sec in block)Cores-VeeR-EH1
dir block - (0.6 sec in block)
sh - (0.39 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config -o /jenkins/processor_ci_utils/labels
stage - (46 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (45 sec in block)
parallel - (45 sec in block)
parallel block (Branch: digilent_arty_a7_100t) - (44 sec in block)
stage - (44 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (43 sec in block)
lock - (43 sec in block)digilent_arty_a7_100t
lock block - (42 sec in block)
stage - (40 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (40 sec in block)
dir - (39 sec in block)Cores-VeeR-EH1
dir block - (39 sec in block)
echo - (0.17 sec in self)Starting synthesis for FPGA digilent_arty_a7_100t.
sh - (39 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p Cores-VeeR-EH1 -b digilent_arty_a7_100t
stage - (0.96 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (0.4 sec in block)
getContext - (0.17 sec in self)
stage - (0.64 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (0.35 sec in block)
getContext - (0.15 sec in self)
stage - (0.75 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.54 sec in block)
junit - (0.27 sec in self)**/*.xml