Console Output

Started by timer
[Pipeline] Start of Pipeline
[Pipeline] node
Running on Jenkins in /var/jenkins_home/workspace/Cores-VeeR-EH1
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone)
[Pipeline] sh
+ rm -rf Cores-VeeR-EH1
[Pipeline] sh
+ git clone --recursive https://github.com/chipsalliance/Cores-VeeR-EH1 Cores-VeeR-EH1
Cloning into 'Cores-VeeR-EH1'...
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Simulation)
[Pipeline] dir
Running in /var/jenkins_home/workspace/Cores-VeeR-EH1/Cores-VeeR-EH1
[Pipeline] {
[Pipeline] sh
+ iverilog -o simulation.out -g2012 -s veer -I design/include design/dmi/dmi_jtag_to_core_sync.v design/dmi/dmi_wrapper.v design/dma_ctrl.sv design/mem.sv design/pic_ctrl.sv design/veer.sv design/veer_wrapper.sv design/dbg/dbg.sv design/dec/dec.sv design/dec/dec_decode_ctl.sv design/dec/dec_gpr_ctl.sv design/dec/dec_ib_ctl.sv design/dec/dec_tlu_ctl.sv design/dec/dec_trigger.sv design/dmi/rvjtag_tap.sv design/exu/exu.sv design/exu/exu_alu_ctl.sv design/exu/exu_div_ctl.sv design/exu/exu_mul_ctl.sv design/ifu/ifu.sv design/ifu/ifu_aln_ctl.sv design/ifu/ifu_bp_ctl.sv design/ifu/ifu_compress_ctl.sv design/ifu/ifu_ic_mem.sv design/ifu/ifu_iccm_mem.sv design/ifu/ifu_ifc_ctl.sv design/ifu/ifu_mem_ctl.sv design/include/veer_types.sv design/lib/ahb_to_axi4.sv design/lib/axi4_to_ahb.sv design/lib/beh_lib.sv design/lib/mem_lib.sv design/lib/svci_to_axi4.sv design/lsu/lsu.sv design/lsu/lsu_addrcheck.sv design/lsu/lsu_bus_buffer.sv design/lsu/lsu_bus_intf.sv design/lsu/lsu_clkdomain.sv design/lsu/lsu_dccm_ctl.sv design/lsu/lsu_dccm_mem.sv design/lsu/lsu_ecc.sv design/lsu/lsu_lsc_ctl.sv design/lsu/lsu_trigger.sv
/var/jenkins_home/workspace/Cores-VeeR-EH1/Cores-VeeR-EH1@tmp/durable-3b77007c/script.sh.copy: 1: iverilog: not found
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Build Pipeline)
Stage "FPGA Build Pipeline" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] parallel
[Pipeline] { (Branch: colorlight_i9)
[Pipeline] { (Branch: digilent_nexys4_ddr)
[Pipeline] stage
[Pipeline] { (colorlight_i9)
[Pipeline] stage
[Pipeline] { (digilent_nexys4_ddr)
Stage "colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
Stage "digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] stage
[Pipeline] { (Síntese e PnR)
[Pipeline] stage
[Pipeline] { (Síntese e PnR)
Stage "colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
Stage "digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash colorlight_i9)
[Pipeline] stage
[Pipeline] { (Flash digilent_nexys4_ddr)
Stage "colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
Stage "digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Teste colorlight_i9)
[Pipeline] stage
[Pipeline] { (Teste digilent_nexys4_ddr)
Stage "colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
Stage "digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] }
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] }
Failed in branch colorlight_i9
[Pipeline] }
Failed in branch digilent_nexys4_ddr
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Declarative: Post Actions)
[Pipeline] dir
Running in /var/jenkins_home/workspace/Cores-VeeR-EH1/Cores-VeeR-EH1
[Pipeline] {
[Pipeline] sh
+ rm -rf LICENSE README.md configs design docs release-notes.md testbench tools veer.core
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
ERROR: script returned exit code 127
Finished: FAILURE