Console Output

+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p Cores-SweRV -b digilent_arty_a7_100t
[LOCK] Criado: run.lock
File 'processor_ci_defines.vh' generated for board: 'digilent_arty_a7_100t'.
Final configuration file generated at /var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/build_digilent_arty_a7_100t.tcl
[LOCK] Removido: run.lock
Error executing Makefile.
ERROR: [Synth 8-9263] cannot open include file 'pic_map_auto.h' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/pic_ctrl.sv:453]
ERROR: [Synth 8-10157] use of undefined macro 'RV_DMA_BUS_TAG' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/dma_ctrl.sv:35]
ERROR: [Synth 8-10157] use of undefined macro 'RV_PIC_TOTAL_INT_PLUS1' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/include/global.h:16]
ERROR: [Synth 8-2716] syntax error near ';' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/include/global.h:16]
ERROR: [Synth 8-10157] use of undefined macro 'RV_DCCM_BITS' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/include/global.h:18]
ERROR: [Synth 8-2716] syntax error near ';' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/include/global.h:18]
ERROR: [Synth 8-10157] use of undefined macro 'RV_DCCM_BANK_BITS' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/include/global.h:19]
ERROR: [Synth 8-2716] syntax error near ';' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/include/global.h:19]
ERROR: [Synth 8-10157] use of undefined macro 'RV_DCCM_NUM_BANKS' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/include/global.h:20]
ERROR: [Synth 8-2716] syntax error near ';' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/include/global.h:20]
ERROR: [Synth 8-10157] use of undefined macro 'RV_DCCM_DATA_WIDTH' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/include/global.h:21]
ERROR: [Synth 8-2716] syntax error near ';' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/include/global.h:21]
ERROR: [Synth 8-10157] use of undefined macro 'RV_DCCM_FDATA_WIDTH' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/include/global.h:22]
ERROR: [Synth 8-2716] syntax error near ';' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/include/global.h:22]
ERROR: [Synth 8-10157] use of undefined macro 'RV_DCCM_BYTE_WIDTH' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/include/global.h:23]
ERROR: [Synth 8-2716] syntax error near ';' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/include/global.h:23]
ERROR: [Synth 8-10157] use of undefined macro 'RV_DCCM_ECC_WIDTH' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/include/global.h:24]
ERROR: [Synth 8-2716] syntax error near ';' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/include/global.h:24]
ERROR: [Synth 8-10157] use of undefined macro 'RV_LSU_NUM_NBLOAD' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/include/global.h:26]
ERROR: [Synth 8-2716] syntax error near ';' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/include/global.h:26]
ERROR: [Synth 8-439] module 'processorci_top' not found
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
make: *** [/eda/processor_ci/makefiles/digilent_arty_a7_100t.mk:12: digilent_arty_a7_100t.bit] Error 1

Traceback (most recent call last):
  File "/eda/processor_ci/main.py", line 142, in <module>
    main(
  File "/eda/processor_ci/main.py", line 89, in main
    build(build_file_path, board_name, toolchain_path)
  File "/eda/processor_ci/core/fpga.py", line 296, in build
    raise subprocess.CalledProcessError(process.returncode, 'make')
subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2.