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Start of Pipeline - (32 sec in block)
node - (31 sec in block)
node block - (30 sec in block)
stage - (5.1 sec in block)Git Clone
stage block (Git Clone) - (4.1 sec in block)
sh - (0.77 sec in self)rm -rf Cores-SweRV
sh - (2.9 sec in self)git clone --recursive https://github.com/chipsalliance/Cores-SweRV Cores-SweRV
stage - (4.7 sec in block)Simulation
stage block (Simulation) - (3 sec in block)
dir - (1.9 sec in block)Cores-SweRV
dir block - (1.2 sec in block)
sh - (0.74 sec in self)
stage - (17 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (17 sec in block)
getContext - (0.68 sec in self)
parallel - (15 sec in block)
parallel block (Branch: colorlight_i9) - (79 ms in block)
stage - (13 sec in block)colorlight_i9
stage block (colorlight_i9) - (13 sec in block)
getContext - (1.5 sec in self)
stage - (3.9 sec in block)Síntese e PnR
stage block (Síntese e PnR) - (1.4 sec in block)
getContext - (0.44 sec in self)
stage - (3.8 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (1.3 sec in block)
getContext - (0.4 sec in self)
stage - (1.9 sec in block)Teste colorlight_i9
stage block (Teste colorlight_i9) - (1.1 sec in block)
getContext - (0.19 sec in self)
parallel block (Branch: digilent_nexys4_ddr) - (14 sec in block)
stage - (13 sec in block)digilent_nexys4_ddr
stage block (digilent_nexys4_ddr) - (12 sec in block)
getContext - (1.3 sec in self)
stage - (4 sec in block)Síntese e PnR
stage block (Síntese e PnR) - (1.6 sec in block)
getContext - (0.35 sec in self)
stage - (3.7 sec in block)Flash digilent_nexys4_ddr
stage block (Flash digilent_nexys4_ddr) - (1.5 sec in block)
getContext - (0.35 sec in self)
stage - (1.6 sec in block)Teste digilent_nexys4_ddr
stage block (Teste digilent_nexys4_ddr) - (0.99 sec in block)
getContext - (0.16 sec in self)
stage - (1.7 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (1.5 sec in block)
dir - (0.95 sec in block)Cores-SweRV
dir block - (0.67 sec in block)
sh - (0.43 sec in self)rm -rf *