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Started by timer
[Pipeline] Start of Pipeline
[Pipeline] node
Running on Jenkins in /var/jenkins_home/workspace/Cores-SweRV
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone)
[Pipeline] sh
+ rm -rf Cores-SweRV
[Pipeline] sh
+ git clone --recursive --depth=1 https://github.com/chipsalliance/Cores-SweRV Cores-SweRV
Cloning into 'Cores-SweRV'...
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Simulation)
[Pipeline] dir
Running in /var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV
[Pipeline] {
[Pipeline] echo
simulation not supported for System Verilog files
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Utilities)
[Pipeline] dir
Running in /var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV
[Pipeline] {
[Pipeline] sh
+ pwd
+ python3 /eda/processor_ci/core/labeler_prototype.py -d /var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV -c /eda/processor_ci/config.json -o /jenkins/processor_ci_utils/labels
Trying to read file: /var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/mem.sv
Trying to read file: /var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/dmi/dmi_jtag_to_core_sync.v
Trying to read file: /var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/dmi/dmi_wrapper.v
Cache-related signals in mem.sv
Cache-related signals in dma_ctrl.sv
Cache-related signals in veer_wrapper.sv
Cache-related signals in veer.sv
Cache-related signals in axi4_to_ahb.sv
Cache-related signals in mem_lib.sv
Cache-related signals in ahb_to_axi4.sv
Cache-related signals in lsu.sv
Cache-related signals in lsu_clkdomain.sv
Cache-related signals in lsu_lsc_ctl.sv
Cache-related signals in lsu_trigger.sv
Cache-related signals in lsu_addrcheck.sv
Cache-related signals in lsu_stbuf.sv
Cache-related signals in lsu_bus_intf.sv
Cache-related signals in lsu_dccm_ctl.sv
Cache-related signals in lsu_bus_buffer.sv
Cache-related signals in lsu_ecc.sv
Cache-related signals in dec_ib_ctl.sv
Cache-related signals in dec_decode_ctl.sv
Cache-related signals in dec_tlu_ctl.sv
Cache-related signals in dec.sv
Cache-related signals in dbg.sv
Cache-related signals in veer_types.sv
Cache-related signals in ifu_mem_ctl.sv
Cache-related signals in ifu_ifc_ctl.sv
Cache-related signals in ifu_bp_ctl.sv
Cache-related signals in ifu.sv
Cache-related signals in ifu_aln_ctl.sv
Cache-related signals in ifu_ic_mem.sv
Cache-related signals in exu.sv
Cache-related signals in exu_mul_ctl.sv
Cache-related signals in exu_div_ctl.sv
Cache-related signals in exu_alu_ctl.sv
Results saved to /jenkins/processor_ci_utils/labels/Cores-SweRV.json
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Build Pipeline)
[Pipeline] parallel
[Pipeline] { (Branch: colorlight_i9)
[Pipeline] { (Branch: digilent_arty_a7_100t)
[Pipeline] stage
[Pipeline] { (colorlight_i9)
[Pipeline] stage
[Pipeline] { (digilent_arty_a7_100t)
[Pipeline] lock
Trying to acquire lock on [Resource: colorlight_i9]
Resource [colorlight_i9] did not exist. Created.
Lock acquired on [Resource: colorlight_i9]
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [Resource: digilent_arty_a7_100t]
Resource [digilent_arty_a7_100t] did not exist. Created.
Lock acquired on [Resource: digilent_arty_a7_100t]
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Synthesis and PnR)
[Pipeline] stage
[Pipeline] { (Synthesis and PnR)
[Pipeline] dir
Running in /var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV
[Pipeline] {
[Pipeline] dir
Running in /var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV
[Pipeline] {
[Pipeline] echo
Starting synthesis for FPGA colorlight_i9.
[Pipeline] sh
[Pipeline] echo
+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p Cores-SweRV -b colorlight_i9
Starting synthesis for FPGA digilent_arty_a7_100t.
[Pipeline] sh
+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p Cores-SweRV -b digilent_arty_a7_100t
Final configuration file generated at /var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/build_colorlight_i9.tcl
Error executing Makefile.
ERROR: Error when parsing design. Aborting!
make: *** [/eda/processor_ci/makefiles/colorlight_i9.mk:12: colorlight_i9.json] Error 1

Traceback (most recent call last):
  File "/eda/processor_ci/main.py", line 135, in <module>
    main(
  File "/eda/processor_ci/main.py", line 82, in main
    build(build_file_path, board_name, toolchain_path)
  File "/eda/processor_ci/core/fpga.py", line 307, in build
    raise subprocess.CalledProcessError(process.returncode, 'make')
subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2.
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash colorlight_i9)
Stage "Flash colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Test colorlight_i9)
Stage "Test colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Lock released on resource [Resource: colorlight_i9]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Failed in branch colorlight_i9
Final configuration file generated at /var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/build_digilent_arty_a7_100t.tcl
Error executing Makefile.
ERROR: [Synth 8-9263] cannot open include file 'global.h' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/dma_ctrl.sv:113]
ERROR: [Synth 8-9263] cannot open include file 'global.h' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/mem.sv:93]
ERROR: [Synth 8-9263] cannot open include file 'global.h' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/pic_ctrl.sv:49]
ERROR: [Synth 8-9263] cannot open include file 'pic_map_auto.h' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/pic_ctrl.sv:453]
ERROR: [Synth 8-9263] cannot open include file 'global.h' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/veer.sv:386]
ERROR: [Synth 8-9263] cannot open include file 'build.h' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/veer_wrapper.sv:23]
ERROR: [Synth 8-9263] cannot open include file 'global.h' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/veer_wrapper.sv:331]
ERROR: [Synth 8-9263] cannot open include file 'global.h' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/dbg/dbg.sv:118]
ERROR: [Synth 8-9263] cannot open include file 'global.h' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/dec/dec_ib_ctl.sv:109]
ERROR: [Synth 8-9263] cannot open include file 'global.h' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/ifu/ifu_aln_ctl.sv:112]
ERROR: [Synth 8-9263] cannot open include file 'global.h' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/ifu/ifu_ic_mem.sv:62]
ERROR: [Synth 8-9263] cannot open include file 'global.h' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/ifu/ifu_iccm_mem.sv:44]
ERROR: [Synth 8-9263] cannot open include file 'global.h' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/ifu/ifu_mem_ctl.sv:191]
ERROR: [Synth 8-9263] cannot open include file 'global.h' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/lsu/lsu.sv:183]
ERROR: [Synth 8-9263] cannot open include file 'global.h' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/lsu/lsu_addrcheck.sv:53]
ERROR: [Synth 8-9263] cannot open include file 'global.h' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/lsu/lsu_bus_buffer.sv:189]
ERROR: [Synth 8-9263] cannot open include file 'global.h' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/lsu/lsu_bus_intf.sv:178]
ERROR: [Synth 8-9263] cannot open include file 'global.h' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/lsu/lsu_dccm_ctl.sv:104]
ERROR: [Synth 8-9263] cannot open include file 'global.h' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/lsu/lsu_dccm_mem.sv:51]
ERROR: [Synth 8-10157] use of undefined macro 'RV_DMA_BUS_TAG' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/dma_ctrl.sv:35]
ERROR: [Synth 8-9263] cannot open include file 'global.h' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/dma_ctrl.sv:113]
ERROR: [Synth 8-10157] use of undefined macro 'RV_DCCM_SADR' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/dma_ctrl.sv:374]
ERROR: [Synth 8-10157] use of undefined macro 'RV_DCCM_SIZE' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/dma_ctrl.sv:375]
ERROR: [Synth 8-10157] use of undefined macro 'RV_PIC_BASE_ADDR' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/dma_ctrl.sv:395]
ERROR: [Synth 8-10157] use of undefined macro 'RV_PIC_SIZE' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/dma_ctrl.sv:396]
ERROR: [Synth 8-36] 'DMA_BUF_DEPTH' is not declared [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/dma_ctrl.sv:115]
ERROR: [Synth 8-35] 'DMA_BUS_TAG' is not a constant [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/dma_ctrl.sv:136]
ERROR: [Synth 8-9960] range must be bounded by constant expressions [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/dma_ctrl.sv:136]
ERROR: [Synth 8-35] 'DMA_BUS_TAG' is not a constant [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/dma_ctrl.sv:197]
ERROR: [Synth 8-9960] range must be bounded by constant expressions [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/dma_ctrl.sv:197]
ERROR: [Synth 8-35] 'DMA_BUS_TAG' is not a constant [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/dma_ctrl.sv:206]
ERROR: [Synth 8-9960] range must be bounded by constant expressions [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/dma_ctrl.sv:206]
ERROR: [Synth 8-35] 'DMA_BUS_TAG' is not a constant [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/dma_ctrl.sv:214]
ERROR: [Synth 8-9960] range must be bounded by constant expressions [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/dma_ctrl.sv:214]
ERROR: [Synth 8-35] 'DMA_BUS_TAG' is not a constant [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/dma_ctrl.sv:228]
ERROR: [Synth 8-9960] range must be bounded by constant expressions [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/dma_ctrl.sv:228]
ERROR: [Synth 8-35] 'DMA_BUS_TAG' is not a constant [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/dma_ctrl.sv:284]
ERROR: [Synth 8-9960] range must be bounded by constant expressions [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/dma_ctrl.sv:284]
ERROR: [Synth 8-439] module 'processorci_top' not found
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
make: *** [/eda/processor_ci/makefiles/digilent_arty_a7_100t.mk:12: digilent_arty_a7_100t.bit] Error 1

Traceback (most recent call last):
  File "/eda/processor_ci/main.py", line 135, in <module>
    main(
  File "/eda/processor_ci/main.py", line 82, in main
    build(build_file_path, board_name, toolchain_path)
  File "/eda/processor_ci/core/fpga.py", line 307, in build
    raise subprocess.CalledProcessError(process.returncode, 'make')
subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2.
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash digilent_arty_a7_100t)
Stage "Flash digilent_arty_a7_100t" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Test digilent_arty_a7_100t)
Stage "Test digilent_arty_a7_100t" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Lock released on resource [Resource: digilent_arty_a7_100t]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Failed in branch digilent_arty_a7_100t
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Declarative: Post Actions)
[Pipeline] junit
Recording test results
No test report files were found. Configuration error?
Error when executing always post condition:
Also:   org.jenkinsci.plugins.workflow.actions.ErrorAction$ErrorId: 9d7307c9-4702-48a3-af33-295fcf106b42
hudson.AbortException: No test report files were found. Configuration error?
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser$ParseResultCallable.invoke(JUnitParser.java:253)
	at hudson.FilePath.act(FilePath.java:1234)
	at hudson.FilePath.act(FilePath.java:1217)
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser.parseResult(JUnitParser.java:146)
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parse(JUnitResultArchiver.java:177)
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parseAndSummarize(JUnitResultArchiver.java:282)
	at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:62)
	at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:27)
	at PluginClassLoader for workflow-step-api//org.jenkinsci.plugins.workflow.steps.SynchronousNonBlockingStepExecution.lambda$start$0(SynchronousNonBlockingStepExecution.java:49)
	at java.base/java.util.concurrent.Executors$RunnableAdapter.call(Unknown Source)
	at java.base/java.util.concurrent.FutureTask.run(Unknown Source)
	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(Unknown Source)
	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(Unknown Source)
	at java.base/java.lang.Thread.run(Unknown Source)

[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
ERROR: script returned exit code 1
Finished: FAILURE