+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p Cores-SweRV -b digilent_arty_a7_100t
Final configuration file generated at /var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/build_digilent_arty_a7_100t.tcl
Error executing Makefile.
ERROR: [Synth 8-9263] cannot open include file 'global.h' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/dma_ctrl.sv:113]
ERROR: [Synth 8-9263] cannot open include file 'global.h' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/mem.sv:93]
ERROR: [Synth 8-9263] cannot open include file 'global.h' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/pic_ctrl.sv:49]
ERROR: [Synth 8-9263] cannot open include file 'pic_map_auto.h' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/pic_ctrl.sv:453]
ERROR: [Synth 8-9263] cannot open include file 'global.h' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/veer.sv:386]
ERROR: [Synth 8-9263] cannot open include file 'build.h' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/veer_wrapper.sv:23]
ERROR: [Synth 8-9263] cannot open include file 'global.h' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/veer_wrapper.sv:331]
ERROR: [Synth 8-9263] cannot open include file 'global.h' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/dbg/dbg.sv:118]
ERROR: [Synth 8-9263] cannot open include file 'global.h' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/dec/dec_ib_ctl.sv:109]
ERROR: [Synth 8-9263] cannot open include file 'global.h' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/ifu/ifu_aln_ctl.sv:112]
ERROR: [Synth 8-9263] cannot open include file 'global.h' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/ifu/ifu_ic_mem.sv:62]
ERROR: [Synth 8-9263] cannot open include file 'global.h' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/ifu/ifu_iccm_mem.sv:44]
ERROR: [Synth 8-9263] cannot open include file 'global.h' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/ifu/ifu_mem_ctl.sv:191]
ERROR: [Synth 8-9263] cannot open include file 'global.h' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/lsu/lsu.sv:183]
ERROR: [Synth 8-9263] cannot open include file 'global.h' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/lsu/lsu_addrcheck.sv:53]
ERROR: [Synth 8-9263] cannot open include file 'global.h' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/lsu/lsu_bus_buffer.sv:189]
ERROR: [Synth 8-9263] cannot open include file 'global.h' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/lsu/lsu_bus_intf.sv:178]
ERROR: [Synth 8-9263] cannot open include file 'global.h' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/lsu/lsu_dccm_ctl.sv:104]
ERROR: [Synth 8-9263] cannot open include file 'global.h' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/lsu/lsu_dccm_mem.sv:51]
ERROR: [Synth 8-10157] use of undefined macro 'RV_DMA_BUS_TAG' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/dma_ctrl.sv:35]
ERROR: [Synth 8-9263] cannot open include file 'global.h' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/dma_ctrl.sv:113]
ERROR: [Synth 8-10157] use of undefined macro 'RV_DCCM_SADR' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/dma_ctrl.sv:374]
ERROR: [Synth 8-10157] use of undefined macro 'RV_DCCM_SIZE' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/dma_ctrl.sv:375]
ERROR: [Synth 8-10157] use of undefined macro 'RV_PIC_BASE_ADDR' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/dma_ctrl.sv:395]
ERROR: [Synth 8-10157] use of undefined macro 'RV_PIC_SIZE' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/dma_ctrl.sv:396]
ERROR: [Synth 8-36] 'DMA_BUF_DEPTH' is not declared [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/dma_ctrl.sv:115]
ERROR: [Synth 8-35] 'DMA_BUS_TAG' is not a constant [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/dma_ctrl.sv:136]
ERROR: [Synth 8-9960] range must be bounded by constant expressions [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/dma_ctrl.sv:136]
ERROR: [Synth 8-35] 'DMA_BUS_TAG' is not a constant [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/dma_ctrl.sv:197]
ERROR: [Synth 8-9960] range must be bounded by constant expressions [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/dma_ctrl.sv:197]
ERROR: [Synth 8-35] 'DMA_BUS_TAG' is not a constant [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/dma_ctrl.sv:206]
ERROR: [Synth 8-9960] range must be bounded by constant expressions [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/dma_ctrl.sv:206]
ERROR: [Synth 8-35] 'DMA_BUS_TAG' is not a constant [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/dma_ctrl.sv:214]
ERROR: [Synth 8-9960] range must be bounded by constant expressions [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/dma_ctrl.sv:214]
ERROR: [Synth 8-35] 'DMA_BUS_TAG' is not a constant [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/dma_ctrl.sv:228]
ERROR: [Synth 8-9960] range must be bounded by constant expressions [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/dma_ctrl.sv:228]
ERROR: [Synth 8-35] 'DMA_BUS_TAG' is not a constant [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/dma_ctrl.sv:284]
ERROR: [Synth 8-9960] range must be bounded by constant expressions [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/dma_ctrl.sv:284]
ERROR: [Synth 8-439] module 'processorci_top' not found
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
make: *** [/eda/processor_ci/makefiles/digilent_arty_a7_100t.mk:12: digilent_arty_a7_100t.bit] Error 1
Traceback (most recent call last):
File "/eda/processor_ci/main.py", line 135, in <module>
main(
File "/eda/processor_ci/main.py", line 82, in main
build(build_file_path, board_name, toolchain_path)
File "/eda/processor_ci/core/fpga.py", line 307, in build
raise subprocess.CalledProcessError(process.returncode, 'make')
subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2.
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